Cell microprocessor implementations: Difference between revisions

Revision as of 18:03, 25 February 2007

Revision as of 22:33, 14 March 2007

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The most likely design node for a future Cell processor is the upcoming 65nm node in which IBM and Toshiba have already invested great sums of money. <!-- found scrap on the Inquirer that Sony and Tosh committed $190 m to achieve some advanced generation ahead of schedule but never reported back on progress, not worth referencing formally sooo it becomes "great [unsubstantiated] sums of money" --> All things remaining equal, a reduction to 65 nm would reduce the existing 230 mm² die based on the 90 nm process to half its current size, about 120 mm², greatly reducing IBM's manufacturing cost as well.

On 12th of March 2007, IBM announced that it started producing 65nm Cells in East Fishkill. The chips produced there are apparently only for IBMs own Cell [Blade Computing_blade] servers, a timeframe for integration of these chips into the [[Playstation 3]] has not yet been announced.

Alternately, IBM could elect to partially redesign the chip to take advantage of additional silicon area. The Cell architecture already makes explicit provisions for the size of the local store to vary across implementations. A chip-level interface is available to the programmer to determine local store capacity, which is always an exact binary power.

IBMs news release is scarse on technical details. So far it is only known that these 65nm-Cells clock up to 6 GHz and run on 1.3V core voltage, as demonstrated on the [[ISSCC]] 2007. This would give the chip a theoretical peak performance of 384 GLFOPS in single precision, a significant improvement to the 204.8 GFLOPS peak that a 3.2 GHz Cell could provide with 8 active SPUs. IBM further announced it implemented new power-saving features and a dual power supply for the SRAM array. Further improvements remain shady so far, but this version is not yet the rumoured "Cell+" with enhanced Double Precision floating point performance, which is still scheduled for 2008 according to the [http://www-5.ibm.com/at/symposium/pdf/00_Collaborative_Innovation_and_the_Cell_Broadband_Engine.pdf Roadmap].

So far this seems to be a pretty straighforward [[Die_(integrated_circuit)|die]]-shrink, as the size of the Local Store RAM and number of SPUs remain the same. This chip should significantly reduce power consumption and be cheaper to produce thanks to the much smaller die-size.

Alternately, IBM could elect to partially redesign the chip to take advantage of additional silicon area in future revisions. The Cell architecture already makes explicit provisions for the size of the local store to vary across implementations. A chip-level interface is available to the programmer to determine local store capacity, which is always an exact binary power.

Based on the reported die area of 30% for the local store in the 90 nm edition, it would be feasible to double the local store to 512&nbsp;KiB per SPU leaving the total die area devoted to the SPU processors roughly unchanged. In this scenario, the SPU area devoted to the local store would increase to 60% while other areas shrink by half. Going this route would reduce heat, and increase performance on memory intensive workloads, but without yielding IBM much if any reduction in cost of manufacture.