Multithreading (computer architecture): Difference between revisions

Revision as of 18:32, 7 April 2007

Revision as of 18:33, 7 April 2007

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For example:

# Cycle i, : instruction j from thread A is issued

# Cycle i+1,: instruction j+1 from thread A is issued

# Cycle i+2,: instruction j+2 from thread A is issued, load instruction which misses in all caches

# Cycle i+3,: thread scheduler invoked, switches to thread B

# Cycle i+4,: instruction k from thread B is issued

# Cycle i+5,: instruction k+1 from thread B is issued