Cell microprocessor implementations: Difference between revisions

Revision as of 04:57, 9 April 2008

Revision as of 23:10, 30 April 2008

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On 12th of March 2007, IBM announced that it started producing 65nm Cells in its East Fishkill fab. The chips produced there are apparently only for IBMs own Cell [[Computing blade|blade]] servers, a timeframe for integration of these chips into the [[Playstation 3]] has not yet been announced.

IBMs news release is scarce on technical details. So far it is only known that these 65nm-Cells clock up to 6 GHz and run on 1.3V core voltage, as [http://news.spong.com/article/11413?cb=936 demonstrated] on the [[ISSCC]] 2007. This would give the chip a theoretical peak performance of 384 GLFOPSGFLOPS in single precision, a significant improvement to the 204.8 GFLOPS peak that a 90nm 3.2 GHz Cell could provide with 8 active SPUs. IBM further announced it implemented new power-saving features and a dual power supply for the SRAM array. Further improvements remain shady so far, but this version is not yet the rumoured "Cell+" with enhanced Double Precision floating point performance, which is still scheduled for 2008 according to the [http://www-5.ibm.com/at/symposium/pdf/00_Collaborative_Innovation_and_the_Cell_Broadband_Engine.pdf Roadmap].

So far this seems to be a pretty straightforward [[Die (integrated circuit)|die]]-shrink, as the size of the Local Store RAM and number of SPUs remain the same. This chip should significantly reduce power consumption and be cheaper to produce thanks to the much smaller die-size.