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===Stage 1: issue===
In the Issueissue stage, instructions are issued for execution if all operands and reservation stations are ready or else they are stalled. Registers are renamed in this step, eliminating WAR and WAW hazards. ▼
*Retrieve the next instruction from the head of the instruction queue . If the instruction operands are currently in the registers▼▲In the Issue stage, instructions are issued for execution if all operands and reservation stations are ready or else they are stalled. Registers are renamed in this step, eliminating WAR and WAW hazards.
**If there is a matching empty reservation station ( i.e., functional unit is available) then: issue the instruction▼
**Else, there is not a matching empty reservation station ( i.e., functional unit is not available) then: stall the instruction until a station or buffer is free▼▲*Retrieve the next instruction from the head of the instruction queue
* *UseElse, the operands are not in the registers, then: use virtual values, the functional unit calculating the real value, to keep track of the functional units that will produce the operands ▼*If the instruction operands are currently in the registers
▲**If there is a matching empty reservation station (functional unit is available)
***Issue the instruction
▲**Else, there is not a matching empty reservation station (functional unit is not available)
***Stall the instruction until a station or buffer is free
*Else, the operands are not in the registers
▲**Use virtual values, the functional unit calculating the real value, to keep track of the functional units that will produce the operands
===Stage 2: execute===
In the Executeexecute stage, the instruction operations are carried out. Instructions are delayed in this step until all of their operands are available, eliminating RAW hazards. Program correctness is maintained through effective address calculation to prevent hazards through memory.
*#If one or more of the operands is not yet available then: wait for operand to become available on the CDB.
*#When all operands are available , then: if the instruction is a load or store▼**Monitor the common data bus (CDB) while waiting for it to be computed
***##Compute the effective address when the base register is available , and place it in the load/store buffer▼**Place operands into corresponding reservation station when they become available
##* ***ExecuteIf the instruction is a load then: execute as soon as the memory unit is available ▼
▲*When all operands are available
##**IfElse, if the instruction is a loadstore orthen: storewait for the value to be stored before sending it to the memory unit
##* **ExecuteElse, the instruction is an ALU operation then: execute the instruction at the corresponding functional unit ▼
▲***Compute the effective address when the base register is available
***Place the effective address in the load or store buffer
***If the instruction is a load
▲****Execute as soon as the memory unit is available
***Else, the instruction is a store
****Wait for the value to be stored before sending it to the memory unit
**Else, the instruction is an ALU operation
▲***Execute the instruction at the corresponding functional unit
===Stage 3: write result===
In the Writewrite Result stage, ALU operations results are written back to registers and store operations are written back to memory.
*If the instruction was an ALU operation
**If the result is available, then: write it on the CDB and from there into the registers and any reservation stations waiting for this result
*Else, if the instruction was a store then: write the data to memory during this step▼***Write it on the CDB and from there into the registers and any reservation stations waiting for this result
▲*Else, if the instruction was a store
**Write the data to memory during this step
== See also ==
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