Programmable interrupt controller: Difference between revisions

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Revision as of 09:23, 26 August 2020

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{{more footnotes|date=September 2013}}

In [[computing]], a '''programmable interrupt controller''' ('''PIC''') is an [[integrated circuit]] that helps [[microprocessor]] (or [[CPU]]) to handle [[Interrupt request (PC architecture)|interrupt requests]] (IRQ) coming from multiple different sources (like external I/O devices) which may come (get fired) simultaneously.<ref>{{Citecite webjournal|title=InterruptA ControllerRevisitation -of anKernel overviewSynchronization {{!}}Schemes
|authors=Christopher Small and ScienceDirectStephen TopicsManley
|url=https://wwwstatic.sciencedirectusenix.comorg/topicspublications/engineeringlibrary/interrupt-controller|access-date=2020-07-26|website=www.sciencedirectproceedings/ana97/full_papers/small/small.comhtml}}</ref> It helps to prioritize IRQs so that CPU switches execution to the most appropriate [[interrupt handler]] (ISR) after the PIC assesses the IRQs' relative priorities. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities.{{Citation needed|date=July 2011}} PICs often allow the cascading of their outputs to inputs between each other. On [[PC architecture]] PIC are typically ebedded into a [[Southbridge (computing)|southbridge chips]] whose internal architecture is defined by chipsets' vendors' standards.

==Common features==