Memory architecture: Difference between revisions

Revision as of 16:55, 16 February 2016

Latest revision as of 14:50, 7 August 2022

(10 intermediate revisions by 7 users not shown)

Line 1:

{{short description|Methods used to implement electronic computer data storage}}

'''Memory architecture''' describes the methods used to implement electronic computer data storage in a manner that is a combination of the fastest, most reliable, most durable, and least expensive way to store and retrieve information. Depending on the specific application, a compromise of one of these requirements may be necessary in order to improve another requirement. Memory architecture also explains how binary digits are converted into electric signals and then stored in the memory cells. And also the structure of a memory cell.

For example, [[dynamic memory]] is commonly used for [[primary data storage]] due to its fast access speed. However dynamic memory must be repeatedly [[memory refresh|refreshed]] with a surge of current millionsdozens of time per second, or the stored data will decay and be lost. [[Flash memory]] allows for long-term storage over a period of years, but it is much slower than dynamic memory, and the static memory storage cells wear out with frequent use.

Similarly, the [[Bus (computing)|data bus]] is often designed to suit specific needs such as serial or parallel data access, and the memory may be designed to provide for [[parity error]] detection or even [[ECC memory|error correction]] in expensive business systems.

The earliest memory architectures are the [[Harvard architecture]], which has two physically separate memories and data paths for program and data, and the [[Princeton architecture]] which uses a single memory and data path for both program and data storage.<ref name="adafruit" />

Most general purpose computers use a hybrid split-cache [[modified Harvard architecture]] that appears to an application program to have a pure Princeton architecture machine with gigabytes of [[virtual memory]], but internally (for speed) it operates with an instruction cache physically separate from a data cache, more like the Harvard model.<ref name="adafruit" >

[https://learn.adafruit.com/memories-of-an-arduino/arduino-memory-architecture "Memory Architectures: Harvard vs Princeton"].

</ref>

DSP systems usually have a specialized, high bandwidth memory subsystem; with no support for memory protection or virtual memory management.<ref>

Robert Oshana.

DSP Software Development Techniques for Embedded and Real-Time Systems.

2006.

"5 - DSP Architectures".

p. 123.

{{doi | 10.1016/B978-075067759-2/50007-7 }}

</ref>

Many [[digital signal processor]]s have 3 physically separate memories and datapaths -- program storage, coefficient storage, and data storage.

A series of [[multiply–accumulate operation]]s fetch from all three areas simultaneously to efficiently implement audio filters as [[convolution]]s.

== See also ==

Line 10 ⟶ 28:

*[[32-bit]]

*[[64-bit]]

*[[Address generation unit]]

*[[Cache-only memory architecture]] (COMA)

*[[Cache memory]]

*[[Conventional memory]]

*[[Deterministic memory]]

*[[Distributed memory]]

*[[Distributed shared memory]] (DSM)

*[[Dual-channel architecture]]

Line 21 ⟶ 41:

*[[Flat memory model]]

*[[Harvard architecture]]

*[[High Memorymemory Areaarea]] (HMA)

*[[Lernmatrix]]

*[[Memory hierarchy]]

*[[Memory level parallelism]]

*[[Memory model (addressing scheme)]]

*[[Memory model (computing)|Memory model]]

*[[Memory protection]]

*[[Memory-disk synchronization]]

*[[Non-Uniform Memory Accessvirtualization]] (NUMA)

*[[Non-uniform memory access]] (NUMA)

*[[PCI memory hole]]

*[[Processor register]]

*[[Registered memory]]

*[[Shared memory (interprocess communication)]]

*[[Shared Memorymemory Architecturearchitecture]] (SMA)

*[[Stack-based memory allocation]]

*[[Tagged architecture]]

*[[Uniform Memorymemory Accessaccess]] (UMA)

*[[Universal memory]]

*[[Video memory]]

*[[von Neumann architecture]]

*[[X86 memory segmentation]]

==References==

{{Reflist}}

[[Category:Computer memory]]