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Similarly, the [[Bus (computing)|data bus]] is often designed to suit specific needs such as serial or parallel data access, and the memory may be designed to provide for [[parity error]] detection or even [[ECC memory|error correction]].
The earliest memory architectures are the [[Harvard architecture]], which has two physically separate memories and data paths for program and data, and the [[Princeton architecture]] which uses a single memory and data path for both program and data storage.<ref name="adafruit" />
Most general purpose computers use a hybrid split-cache [[modified Harvard architecture]] that appears to an application program to have a pure Princeton architecture machine with gigabytes of [[virtual memory]], but internally (for speed) it operates with an instruction cache physically separate from a data cache, more like the Harvard model.<ref name="adafruit" >
[https://learn.adafruit.com/memories-of-an-arduino/arduino-memory-architecture "Memory Architectures: Harvard vs Princeton"].
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DSP systems usually have a specialized, high bandwidth memory subsystem; with no support for memory protection or virtual memory management.<ref>
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{{doi | 10.1016/B978-075067759-2/50007-7 }}
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Many [[digital signal processor]]s have 3 physically separate memories and datapaths -- program storage, coefficient storage, and data storage.
A series of [[multiply–accumulate operation]]s fetch from all three areas simultaneously to efficiently implement audio filters as [[convolution]]s.
== See also ==
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*[[Memory hierarchy]]
*[[Memory level parallelism]]
*[[Memory model (addressing scheme)]]
*[[Memory model (computing)|Memory model]]
*[[Memory protection]]
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