Simple programmable logic device: Difference between revisions

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Revision as of 20:31, 1 February 2022 edit Frankplow (talk \| contribs) 74 edits Propose merger from PAL, PLA, GAL Tag: Reverted ← Previous edit		Latest revision as of 18:20, 26 December 2022 edit undo Klbrain (talk \| contribs) Autopatrolled, Extended confirmed users, New page reviewers 97,828 edits Closing stale February merge proposal; uncontested objection(s) and no support; see Talk:Simple programmable logic device#Merger proposal Tag: Manual revert
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Line 1: ~~{{mergefrom\|Programmable array logic\|Programmable logic array\|Generic array logic\|discuss=Talk:Simple programmable logic device#Merger proposal\|date=February 2022}}~~ {{moreref\|date=November 2012}} A '''simple programmable logic device''' ('''SPLD''') is a [[programmable logic device]] with complexity below that of a [[complex programmable logic device\|complex programmable logic device (CPLD)]].