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{{moreref|date=November 2012}}
A '''simple programmable logic device''' ('''SPLD''') is a [[programmable logic device]] with complexity below that of a [[complex programmable logic device|complex programmable logic device (CPLD)]].
The term commonly refers to devices such as [[read-only memory|ROM]]s, [[programmable array logic|PAL]]s, [[programmable logic array|PLA]]s and [[generic array logic|GAL]]s.
== Basic
Simple programmable logic devices (SPLD) are the simplest, smallest and least-expensive forms of programmable logic devices. SPLDs can be used in boards to replace
They typically comprise 4 to 22 fully connected macrocells. These macrocells typically consist of some combinatorial logic (such as AND OR gates) and a flip-flop. In other words, a small [[Boolean algebra|Boolean logic]] equation can be built within each macrocell. This equation will combine the state of some number of binary inputs into a binary output and, if necessary, store that output in the flip-flop until the next clock edge. Of course, the particulars of the available logic gates and flip-flops are specific to each manufacturer and product family. But the general idea is always the same.
Most SPLDs use either fuses or non-volatile memory cells ([[EPROM]], [[EEPROM]],
These devices are also known as:
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The design inside the chip is flexible, so a change in the logic does not require any rewiring of the board. Rather, simply replacing one PLD with another part that has been programmed with the new design can alter the decoding logic.
==References==
{{cite book
|url= https://www.safaribooksonline.com/library/view/introduction-to-digital/9780470900550/chap1-sec007.html
|first= Mohammed |last= Ferdjallah
|date= 2011
|title= Introduction to Digital Systems: Modeling, Synthesis, and Simulation Using VHDL
|isbn= 9780470900550
|publisher= John Wiley & Sons
|website= Safari Books online
}}
▲ * Simple Programmable Logic Devices (SPLDs)
[[Category:Gate arrays]]
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