Flow to HDL: Difference between revisions

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{{unrefunreferenced|date=May 2012}}

'''Flow to HDL''' tools and methods convert flow-based system design into a [[hardware description language]] (HDL) such as [[VHDL]] or [[Verilog]]. Typically this is a method of creating designs for [[field-programmable gate array]], [[application-specific integrated circuit]] prototyping and [[digital signal processing]] (DSP) design. Flow-based system design is well-suited{{saysaccording whoto whom|date=May 2012}} to field-programmable gate array design as it is easier to specify the innate parallelism of the architecture.

== History==

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== Applications ==

Most applications are ones which take too long with existing supercomputer architectures. These include bioinfomaticsbioinformatics, [[Computational fluid dynamics|CFD]], financial processing and oil and gas survey data analysis. Embedded applications that require high performance or real-time data processing are also an area of use. [[System-on-a-chip]] design can also be done using this flow.

== Examples ==

*Xilinx System Generator from [http://www.Xilinx.com/ Xilinx]

*StarBridge VIVA from defunct <s>[http://www.starbridgesystems.com/ StarBridge Systems]</s>

*Nimbus from defunct <s>[http://www.exsedia.com/ Exsedia]</s>

== External links ==

*[http://www.cse.clrc.ac.uk/disco/publications/FPGA_overview_2.0.pdf]{{dead link|date=October 2017 |bot=InternetArchiveBot |fix-attempted=yes }} an overview of flows by Daresbury Labs.

*[https://web.archive.org/web/20070216180902/http://www.xilinx.com/products/design_tools/logic_design/advanced/esl/index.htm] Xilinx's ESL initiative, some products listed and C to VHDL tools.

== See also ==

{{Commons category}}

* [[ASIC|Application Specific Integrated Circuit]] (ASIC)

* [[C to HDL]]

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* [[Handel-C]]

* [[Icarus Verilog]]

* [[JHDL]]

* [[Lustre (programming language)]]

* [[MyHDL]]