Address decoder: Difference between revisions

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[[Image:2to4demux.svg|thumb|right|The four states of a 2-to-4 Decoderdecoder]]

In [[digital electronics]], an '''address decoder''' is a [[binary decoder]] that has two or more inputs for [[address bus|address]] bits and one or more outputs for device selection signals.<ref name="TAoE">{{cite book| author=[[Paul Horowitz]] and [[Winfield Hill]]| title=[[The Art of Electronics]]| edition=2nd| year=1989| publisher=Cambridge University Press| isbn=978-0-521-37095-0| page=[https://archive.org/details/artofelectronics00horo/page/685 685,766]}}</ref> When the address for a particular device appears on the address inputs, the decoder asserts the selection output for that device. A dedicated, single-output address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.<ref>{{cite book

|author=S. J. Cahill

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An address decoder is a commonly used component in microelectronics that is used to select memory cells in randomly addressable memory devices.

Such a memory cell consists of a fixed number of memory elements or bits. The address decoder is connected to an address bus and reads the address created there. Using a special switching logic, it uses this address to calculate which memory cell is to be accessed. It then selects that cell by selecting it via a special control line. This line is also known as the select line. In dynamic memories ([[Dynamic random-access memory|DRAM]]), there are row and column select lines on the memory matrix, which are controlled by address decoders integrated in the chip.

Depending on the type of decoder, the logic used to select the memory cell can under certain circumstances be programmable.

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For this purpose, the memory modules or memory chips have selection inputs, usually referred to as chip select pin (CS) or chip enable pin (CE) pin. These inputs often have a negative logic function ({{overline|CS}} or {{overline|CE}}), i. H. with an adjacent logical zero (voltage level low) is selected.

The address decoder uses the different combinatorial logic to place the memory modules or chips in the address space of a processor. The memory modules often have a smaller capacity than the address space. In most cases, several modules can be used, even if they are completely identical in structure. It must be ensured that they differ in the address range.

==References==