Address decoder: Difference between revisions

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[[Image:2to4demux.pngsvg|thumb|right|The four states of a 2-to-4 Decoderdecoder]]

In [[digital electronics]], an '''address decoder''' is a [[binary decoder]] circuit that has two or more bitsinputs of anfor [[address bus|address]] as inputsbits and that has one or more outputs for device selection lines as outputssignals.<ref name="TAoE">{{cite book| author=[[Paul Horowitz]] and [[Winfield Hill]]| title=[[The Art of Electronics]]| edition=2nd| year=1989| publisher=Cambridge University Press| isbn=9780521370950978-0-521-37095-0| page=[https://archive.org/details/artofelectronics00horo/page/685 685,766]}}</ref> When the address for a particular device appears on the address businputs, the address decoder asserts the selection lineoutput for that device. A separatededicated, single-deviceoutput address decoder may be incorporated into each device on an address bus, or a single address decoder may serve multiple devices.<ref>{{cite book

|author=S. J. Cahill

|title=Digital and microprocessor engineering

|url=httphttps://books.google.com/books?id=zwJTAAAAMAAJ

|edition=2nd

|year=1993

|publisher=Ellis Horwood

|isbn=9780132133982978-0-13-213398-2

|pages=489–494

|page=489-494

}}</ref>

}}</ref> When a single address decoder serves multiple devices, an address decoder with n address input bits can serve up to 2ⁿ separate devices. Several members of the [[List of 7400 series integrated circuits|7400 series]] of [[integrated circuit]] are address decoders. An example is the 74154 . This address decoder has four address inputs and sixteen (i.e., 2⁴ ) device selector outputs. An address decoder is also referred to as a "[[demultiplexer]]" or "demux," although these terms are more general and can refer to devices other than address decoders. The 74154 mentioned above can be called a "4-to-16 demux."

}}</ref> When aA single address decoder serves multiple devices, an address decoder with n address input bits can serve up to 2ⁿ separate devices. Several members of the [[List of 7400 series integrated circuits|7400 series]] of [[integrated circuit]]s arecan be used as address decoders. AnFor example, iswhen used as an address decoder, the 74154 <ref>[https://assets.nexperia.com/documents/data-sheet/74HC_HCT154.pdf ThisDatasheet addressfor decoder74HCT154]</ref> hasprovides four address inputs and sixteen (i.e., 2⁴ ) device selector outputs. An address decoder is alsoa referredparticular touse of a [[binary decoder]] circuit known as a "[[demultiplexer]]" or "demux," although these terms are more general and can refer to devices other than address decoders. The(the 74154 mentionedis above can becommonly called a "4-to-16 demux.demultiplexer"), which has many other uses besides address decoding.

Address decoders are fundamental building blocks for systems that use buses. They are represented in all integrated circuit families and processes and in all standard [[FPGA]] and [[ASIC]] libraries. They are discussed in introductory textbooks in digital logic design.<ref name="TAoE"/>

Address decoders are fundamental building blocks for systems that use [[Bus (computing)|buses]]. They are represented in all integrated circuit families and processes and in all standard [[FPGA]] and [[Application-specific integrated circuit|ASIC]] libraries. They are discussed in introductory textbooks in digital logic design.<ref name="TAoE"/>

== Address decoder selects the storage cell in a memory ==

An address decoder is a commonly used component in microelectronics that is used to select memory cells in randomly addressable memory devices.

Such a memory cell consists of a fixed number of memory elements or bits. The address decoder is connected to an address bus and reads the address created there. Using a special switching logic, it uses this address to calculate which memory cell is to be accessed. It then selects that cell by selecting it via a special control line. This line is also known as the select line. In dynamic memories ([[Dynamic random-access memory|DRAM]]), there are row and column select lines on the memory matrix, which are controlled by address decoders integrated in the chip.

Depending on the type of decoder, the logic used to select the memory cell can under certain circumstances be programmable.

== Address decoder selects the appropriate memory module ==

An address decoder is also used to select the appropriate one of multiple memory modules or memory chips when a particular address is provided by the processor system's address bus.

For this purpose, the memory modules or memory chips have selection inputs, usually referred to as chip select pin (CS) or chip enable pin (CE) pin. These inputs often have a negative logic function ({{overline|CS}} or {{overline|CE}}), i. H. with an adjacent logical zero (voltage level low) is selected.

The address decoder uses the different combinatorial logic to place the memory modules or chips in the address space of a processor. The memory modules often have a smaller capacity than the address space. In most cases, several modules can be used, even if they are completely identical in structure. It must be ensured that they differ in the address range.

==References==

{{reflist}}

==External links==

*[http://notes.ump.edu.my/fkee/FADHIL%20ABAS/BEE2223/13_Address%20Decoder.ppt Universiti Malaysia Pahang E-Notes]

*[http://web.mit.edu/6.115/www/datasheets/74hc154.pdf Datasheet for 74HC154]

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[[pt:Decodificador de endereços]]