Cell microprocessor implementations: Difference between revisions

Revision as of 00:20, 10 August 2023

Latest revision as of 10:00, 17 August 2023

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On 12 March 2007, IBM announced that it started producing 65 nm Cells in its East Fishkill fab. The chips produced there are apparently only for IBMs own Cell [[Computing blade|blade]] servers, which were the first to get the 65 nm Cells. Sony introduced the third generation of the PS3 in November 2007, the 40GB model without PS2-compatibility which was [https://www.engadget.com/2007/10/30/40gb-ps3-features-65nm-chips-lower-power-consumption/ confirmed] to use the 65 nm Cell. Thanks to the shrunk Cell, power consumption was reduced from 200{{nbsp}}W to 135{{nbsp}}W.

At first it was only known that the 65 nm-Cells clock up to 6 GHz and run on 1.3{{nbsp}}V core voltage, as [http://news.spong.com/article/11413?cb=936 demonstrated] on the [[ISSCC]] 2007. This would have given the chip a theoretical peak performance of 384{{nbsp}}GFLOPS in FP8 quarter precision (48{{nbsp}}GFLOPs in FP64 dual precision), a significant improvement to the 204.8{{nbsp}}GFLOPS peak (25.6{{nbsp}}GFLOPs FP64 dual precision) that a 90 nm 3.2 GHz Cell could provide with 8 active SPUs. IBM further announced it implemented new power-saving features and a dual power supply for the SRAM array. This version was not yet the long-rumoured "Cell+" with enhanced Double Precision floating point performance, which first saw the light of day mid-2008 in the [[IBM Roadrunner|Roadrunner supercomputer]] in the form of [[QS22#Cell based Blades|QS22]] PowerXCell blades. Although IBM talked about and even showed higher-clocked Cells before, clock speed has remained constant at 3.2 GHz, even for the double precision enabled "Cell+" of the Roadrunner. By keeping clockspeed constant, IBM has instead opted to reduce power consumption. PowerXCell clusters even best IBMs [[Blue Gene]] clusters (371{{nbsp}}MFLOPS/watt), which are far more power-efficient already than clusters made up of conventional CPUs (265{{nbsp}}MFLOPS/watt and lower).

===Future editions in CMOS===