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==Use in verification==
Logic simulation may be used as part of the [[Verification and validation|verification]] process in designing hardware.<ref name="ResearchGate">{{cite book |last1=Bombieri |first1=Nicola |last2=Fummi |first2=Franco |last3=Pravadelli |first3=Graziano |title=Hardware Design and Simulation for Verification |series=Lecture Notes in Computer Science |date=May 2006 |pages=1–29 |url=https://www.researchgate.net/publication/221224340}}</ref>
Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design. By allowing the user to interact directly with the design, simulation is a natural way for the designer to get feedback on their design.
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A prospective way to accelerate logic simulation is using [[distributed computing|distributed]] and [[parallel computing|parallel]] computations.<ref>Software system for distributed [[Event-driven programming|event-driven]] logic simulation. Ladyzhensky Y.V., Popoff Y.V. Proceedings of IEEE East-West Design & Test Workshop(EWDTW'05). IEEE EWDTW, 2005, p.119-122 {{ISBN|966-659-113-8}}</ref>
To help gauge the thoroughness of a simulation, tools exist for assessing [[code coverage]],<ref>{{cite
|author=Wang, Tsu-Hua and Tan, Chong Guan
|conference=1995 IEEE International Verilog HDL Conference
|pages=99–104
|year=1995
|publisher=IEEE
|url=https://ieeexplore.ieee.org/document/512503 }}</ref>
functional coverage, finite state machine (FSM) coverage, and many other metrics.<ref>{{cite conference
|title=Coverage analysis techniques for HDL design validation
|author=Jou, Jing-Yang and Liu, Chien-Nan Jimmy
|conference=Asia Pacific CHip Design Languages
|pages=48–55
|year=1999
|url=https://www.researchgate.net/publication/266883269}}</ref>
== Event simulation versus cycle simulation ==
[[Discrete event simulation|Event simulation]] allows the design to contain simple timing information – the delay needed for a signal to travel from one place to another. During simulation, signal changes are tracked in the form of events. A change at a certain time triggers an event after a certain delay. Events are sorted by the time when they will occur, and when all events for a particular time have been handled, the simulated time is advanced to the time of the next scheduled event. How fast an event simulation runs depends on the number of events to be processed (the amount of activity in the model).<ref>{{cite web |title=Network Modeling and Simulation Environment |url=https://apps.dtic.mil/sti/pdfs/ADA566432.pdf |website=Defense Technical Information Center |access-date=January 1, 2023}}</ref>
While event simulation can provide some feedback regarding signal timing, it is not a replacement for [[static timing analysis]].
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