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==Use in verification==
Logic simulation may be used as part of the [[Verification and validation|verification]] process in designing hardware.<ref name="ResearchGate">{{cite
Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design. By allowing the user to interact directly with the design, simulation is a natural way for the designer to get feedback on their design.
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A prospective way to accelerate logic simulation is using [[distributed computing|distributed]] and [[parallel computing|parallel]] computations.<ref>Software system for distributed [[Event-driven programming|event-driven]] logic simulation. Ladyzhensky Y.V., Popoff Y.V. Proceedings of IEEE East-West Design & Test Workshop(EWDTW'05). IEEE EWDTW, 2005, p.119-122 {{ISBN|966-659-113-8}}</ref>
To help gauge the thoroughness of a simulation, tools exist for assessing [[code coverage]],
|title=Practical code coverage for Verilog
|author=Wang, Tsu-Hua and Tan, Chong Guan
|conference=1995 IEEE International Verilog HDL Conference
|pages=
|year=1995
|publisher=IEEE
|url=https://ieeexplore.ieee.org
functional coverage, finite state machine (FSM) coverage, and many other metrics.<ref>{{cite conference
|title=Coverage analysis techniques for HDL design validation
|author=Jou, Jing-Yang and Liu, Chien-Nan Jimmy
|conference=Asia Pacific CHip Design Languages
|pages=48–55
|year=1999
|url=https://www.researchgate.net/publication/266883269}}</ref>
== Event simulation versus cycle simulation ==
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