Signoff (electronic design automation): Difference between revisions

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{{Short description|Verification stages of electronic designs that must pass before manufacture}}

In the [[electronic design automation|automated]] design of [[integrated circuit]]s, '''signoff''' (also written as '''sign-off''') checks is the collective name given to a series of verification steps that must pass before the design can be [[tapeout|taped out]]. This implies an iterative process involving incremental fixes across the board in one or more check type and retesting the design.

{{Use American English|date = April 2019}}

In the [[electronic design automation|automated]] design of [[integrated circuit]]s, '''signoff''' (also written as '''sign-off''') checks is the collective name given to a series of verification steps that the design must pass before it can be [[Tape-out|taped out]]. This implies an iterative process involving incremental fixes across the board using one or more check types, and then retesting the design. There are two types of sign-off's: [[front-end sign-off]] and [[back-end sign-off]]. After back-end sign-off, the chip goes to fabrication. After listing out all the features in the specification, the verification engineer will write coverage for those features to identify bugs, and send back the RTL design to the designer. Bugs, or defects, can include issues like missing features (comparing the layout to the specification), errors in design (typo and functional errors), etc. When the coverage reaches a maximum percentage then the verification team will sign it off. By using a methodology like UVM, OVM, or VMM, the verification team develops a reusable environment. Nowadays, UVM is more popular than others.

== History ==

During the late 1960s engineers at semiconductor companies like Intel used [[rubylith]] for the production of semiconductor lithography photomasks. Manually drawn [[Circuit diagram|circuit draft schematics]] of the semiconductor devices made by engineers were transeferred manually onto [[Paper size|D-sized]] [[vellum]] sheets by a skilled schematic designer to make a physical layout of the device on a photomask.<ref name=":0">{{Cite journal |date=2001 |title=Recollections of Early Chip Development at Intel |url=https://deramp.com/downloads/mfe_archive/050-Component%20Specifications/Intel/Recollections%20of%20Early%20Chip%20Dev.pdf |journal=Intel Technology Journal |volume=5 |issue=2001 |issn=1535-864X}}</ref>{{r|:0|pp=6}}

The vellum would be later hand-checked and ''signed off'' by the original engineer; all edits to the schematics would also be noted, checked, and, again, ''signed off''.{{r|:0|pp=6}}

== Check types ==

Signoff checks have become more complex as [[VLSI]] designs approach [[32nm22nm]] and [[22nm]]below process nodes, because of the increased impact of previously ignored (or more crudely approximated) second -order effects. There are several categories of signoff checks.

* [[Layout versusVersus schematic|LVSSchematic]] -(LVS) – Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Design rule checking|DRC]] - Also sometimes known as geometric verification, this involves verifying if the design can be reliably [[semiconductor fabrication|manufactured]] given current photolithography limitations. In advanced process nodes, [[Design for manufacturability (IC)|DFM]] rules are upgraded from optional (for better yield) to required.

* [[Layout versus schematic|LVS]] - Also known as schematic verification, this is used to verify that the [[placement (electronic design automation)|placement]] and [[routing (electronic design automation)|routing]] of the [[standard cell]]s in the design has not altered the functionality of the constructed circuit.

* [[Design rule checking|DRC]] -(DRC) – Also sometimes known as geometric verification, this involves verifying if the design can be reliably [[semiconductor fabrication|manufactured]] given current photolithography limitations. In advanced process nodes, [[Design for manufacturability (IC)|DFM]] rules are upgraded from optional (for better yield) to required.

* [[Formal verification]] -– Here, the logical functionality of the post-[[Integrated circuit layout|layout]] netlist (including any layout-driven optimization) is verified against the pre-layout, post-[[logic synthesis|synthesis]] [[netlist]].

* [[Power network design (IC)|Voltage drop]] analysis -– Also known as IR-drop analysis, this check verifies if the [[Power network design (IC)|power grid]] is strong enough to ensure that the [[IC power supply pin|voltage]] representing the binary '''high''' value never dips lower than a set margin (below which the circuit will not function correctly or reliably) due to the combined switching of millions of transistors.

* [[Signal integrity]] analysis - Here, noise due to crosstalk and other issues is analyzed, and its effect on circuit functionality is checked to ensure that capacitive glitches are not large enough to cross the [[threshold voltage]] of gates along the data path.

* [[Signal integrity]] analysis – Here, noise due to crosstalk and other issues is analyzed, and its effect on circuit functionality is checked to ensure that capacitive glitches are not large enough to cross the [[threshold voltage]] of gates along the data path.
* [[Static timing analysis]] (STA) -– Slowly being superseded by [[statistical static timing analysis]] (SSTA), STA is used to verify if all the logic data paths in the design can work at the intended [[clock frequency]], especially under the effects of [[Process corners|on-chip variation]]. STA is run as a replacement for [[SPICE]], because SPICE simulation's runtime makes it infeasible for full-chip analysis modern designs.

* [[Electromigration]] lifetime checks -– To ensure a minimum lifetime of operation at the intended clock frequency without the circuit succumbing to [[electromigration]].

*[[Functional verification|Functional]] Static Sign-off checks – which use search and analysis techniques to check for design failures under all possible test cases; functional static sign-off domains include [[clock ___domain crossing]], reset ___domain crossing and X-propagation.

== Tools ==

A small subset of tools are classified as "golden" or signoff-quality. Categorizing a tool as signoff-quality without vendor-bias is a matter of trial and error, since the accuracy of the tool can only be determined after the design has been fabricated. So, one of the metrics that is in use (and often touted by the tool manufacturer/vendor) is the number of successful tapeouts enabled by the tool in question. It has been argued that this metric is insufficient, ill-defined, and irrelevant for certain tools, especially tools that play only a part in the full flow.<ref>[http{{Cite web|url=https://www.eetimes.com/op/showArticledocument.jhtmlasp?articleIDdoc_id=1142973|title=18305399 EETimes.com: Vendors should count silicon, not tapeout wins]|website=EETimes|access-date=2019-04-03}}</ref>.

While vendors often embellish the ease of end-to-end (typically [[Register transfer level|RTL]] to [[GDSII|GDS]] for [[Application-specific integrated circuit|ASIC]]s, and RTL to [[timing closure]] for [[FPGA]]s) execution through their respective tool suite, most semiconductor design companies use a combination of tools from various vendors (often called "[[best of breed]]" tools) in order to minimize correlation errors pre- and post-silicon.<ref>DeepChip - [http://www.deepchip.com/items/snug07-09.html SNUG survey of physical verification tools].</ref>. Since independent tool evaluation is expensive (single licenses for design tools from major vendors like [[Synopsys]] and [[Cadence Design Systems|Cadence]] may cost tens or hundreds of thousands of dollars) and a risky proposition (if the failed evaluation is done on a production design, resulting in a [[time to market]] delay), it is feasible only for the largest design companies (like [[Intel]], [[International Business Machines|IBM]], [[Freescale Semiconductor|Freescale]], and [[Texas Instruments|TI]]). As a [[value add]], several semiconductor foundries now provide pre-evaluated reference/recommended methodologies (sometimes referred to as "RM" flows) which includes a list of recommended tools, versions, and scripts to move data from one tool to another and automate the entire process.<ref>[http://www.eetimes.com/showArticle.jhtml?articleID=216900259&printable=true TSMC's sign-off flow]</ref>.

This list of vendors and tools is meant to be representative and is not exhaustive:

* DRC/LVS - [https://www.mentor.com/pcb/hyperlynx/electrical-rule-check/drc-editions Mentor HyperLynx DRC Free/Gold], [http://www.mentor.com/products/ic_nanometer_design/verification-signoff/physical-verification/ Mentor Calibre], [http://www.magma-da.com/products-solutions/verification/quartzDRCLVS.aspx Magma Quartz], [httphttps://wwwweb.archive.org/web/20090309103912/http://synopsys.com/tools/implementation/physicalverification/pages/hercules.aspx Synopsys Hercules], [http://www.cadence.com/products/mfg/apv/pages/default.aspx Cadence Assura]

* Voltage drop analysis - [http://www.cadence.com/products/mfg/voltus/pages/default.aspx Cadence Voltus], [https://web.archive.org/web/20090412030004/http://www.apache-da.com/apache-da/Home/ProductsandSolutions/SoCPowerNoiseReliability.html Apache Redhawk], [http://www.magma-da.com/products-solutions/lowpower/QuartzRail.aspx Magma Quartz Rail]

* Signal integrity analysis - [http://w2.cadence.com/datasheets/3073E_CeltIC_DS_Fnl.pdf Cadence CeltIC] (crosstalk noise), [http://www.cadence.com/products/mfg/tempus/pages/default.aspx Cadence Tempus Timing Signoff Solution], [http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx Synopsys PrimeTime SI] (crosstalk delay/noise), [http://www.extreme-da.com/Gold_Time_Suite.html Extreme-DA GoldTime SI] (crosstalk delay/noise)

* Static timing analysis - [http://www.synopsys.com/Tools/Implementation/SignOff/Pages/PrimeTime.aspx Synopsys PrimeTime], [http://www.magma-da.com/products-solutions/verification/quartzssta.aspx Magma Quartz SSTA], [http://www.cadence.com/products/di/ets/pages/default.aspx Cadence ETS], [http://www.cadence.com/products/mfg/tempus/pages/default.aspx Cadence Tempus Timing Signoff Solution], [http://www.extreme-da.com/Gold_Time_Suite.html Extreme-DA GoldTime]

== References ==