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{{WikiProject Computing |importance=Mid |hardware= |hardware-importance=High}}
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==Present tense?==
The tenses are a bit odd here. Maybe they should be unified to present tense unless past tense is actually approriate? <small><span class="autosigned">—Preceding [[Wikipedia:Signatures|unsigned]] comment added by [[User:Qbeep|Qbeep]] ([[User talk:Qbeep|talk]] • [[Special:Contributions/Qbeep|contribs]]) 01:26, 9 April 2009 (UTC)</span></small><!-- Template:Unsigned --> <!--Autosigned by SineBot-->
==Date==
Is the date ("1994-10-10") at the bottom of the page really necessary? It is the date from the [[FOLDOC]] entry that this article is based on, I think. I don't see why it is still relevant. I'm going to remove it, but if it's serving some sort of good purpose, go ahead and put it back. [[User:James Foster|James Foster]] 09:57, 24 Nov 2004 (UTC)
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:[[Amdahl's law]] doesn't seem to say anything about bang-for-the-buck; it discusses the speedup available for a particular program from parallelizing it (which applies to CISC or RISC).
Instead of saying that CISC was succeeded, it would have been more accurate to have said that CISC was succeeded by RISC in the development of modern architectures, and that legacy architectures stopped executing CISC instructions directly and started breaking up the CISC instructions into RISC "micro-operations" as part of their execution. The Intel x86 and the IBM360 architectures fall in this category. The presence of these legacy architectures in desktops, servers, and mainframes is true, but I think that they are RISC systems that have a preprocessor in order to support CISC legacy code. Conceptually speaking, CISC is not a competitor to RISC for the reasons stated above. Amdahl's Law is very important in pipelining, but its general form says that the maximum expected improvement to an overall system is constrainted when only part of the system is improved. Thus devoting logic on a chip to CISC instructions is a poor choice when they are seldom used (due to compilers) and they can not be pipelined (due to widely varying execution times). Basically I think the section fails to mention that RISC won the CISC/RISC war. <span style="font-size: smaller;" class="autosigned">— Preceding [[Wikipedia:Signatures|unsigned]] comment added by [[Special:Contributions/151.151.16.22|151.151.16.22]] ([[User talk:151.151.16.22|talk]]) 19:42, 3 January 2014 (UTC)</span><!-- Template:Unsigned IP --> <!--Autosigned by SineBot-->
:Given that programmers can't write uop code for x86 or z/Architecture, and compilers can't write uop code for x86 or z/Architecture, the "legacy" architectures are still relevant.
:As for how RISCy the micro-operations are, note that, with [http://www.anandtech.com/show/1998/3 micro-operation fusion], the micro-operations aren't quite as micro; that page speaks of combining a compare instruction and a conditional branch into a single micro-op and of combining the load and add micro-ops of ADD [mem], EAX into a single micro-op. The latter is a bit of a move away from the load-store architecture aspect of RISC.
:So the only way in which RISC "won" is that the units of dispatch, scheduling, and execution in modern processors are simpler than some of the instructions in current CISC processors; the units of generated code, however, are still CISC in those processors, even if compilers only use some of the CISCy parts (memory-register and register-memory arithmetic, double-indexing in memory operands, maybe CISCier procedure calls in some cases, maybe decimal and string instructions on z/Architecture or REP/xxx instruction pairs on x86) and ignore the other CISCy parts (which don't get a lot of transistors allocated to them), and even some of the units of dispatch, scheduling, and execution might combine a memory reference and an arithmetic op (micro-operation fusion).
:The only RISC ISA that "won", for general-purpose computing, to the extent of displacing competitors or keeping them out in the first place is ARM (not a lot of Atom smartphones or tablets out there); the others lost in the desktop/laptop market (it'll be interesting to see whether ARM comes back there) and are fighting it out with x86-64 and z/Architecture in the server market. The others lost in the desktop/laptop market largely because Intel (and, to a lesser extent, AMD) had the money to throw transistors at decoders that turned x86 instructions into uop sequences; devoting logic on a chip to doing that is a very good choice if it means that you keep PowerPC, MIPS, SPARC, and PA-RISC out of a lucrative market.
:Another way to think of it is that the first "C" of "CISC" got split into "the stuff that we need to make go fast, because programmers and compilers use it a lot" and "the stuff that's not used enough, so it just has to work, not go fast", with the former stuff made to "go fast" with techniques such as breaking it into uops, and the latter stuff left around, but with the fraction of the chip used to implement it getting smaller over time. That split is a win for some of the ideas that motivated RISC, but with the "reduction" process not, for example, requiring a load-store architecture. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 22:29, 3 January 2014 (UTC)
== instructions or operations? ==
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:::::"a computer in which a single operation (dictated by a single opcode) can execute several low-level operations (such as a load from memory, an arithmetic operation, and a memory store) and/or are capable of multi-step operations or addressing modes within single operations" uses "operation" in two separate senses, so it's potentially confusing. "a computer in which a single operation (dictated by a single opcode) can execute a load from memory, an operation on the loaded data, and a store of the result" is better, although it seems to imply that, to be a CISC processor, you have to be able to do a load ''and'' a store in a single machine operation, and a lot of CISCs don't do that. I might be tempted to just change the opening sentence to say "where single machine operations (specified by a single [[opcode]]) can execute several low-level operations ... and/or are capable of multi-step operations or addressing modes within single machine operations", i.e. just replace "instruction" by "machine operation" and, the first time "machine operation" is used, note that a "machine operation" is what's specified by a single opcode. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 18:56, 15 September 2011 (UTC)
== Requested move 19 May 2017 ==
<div class="boilerplate" style="background-color: #efe; margin: 2em 0 0 0; padding: 0 10px 0 10px; border: 1px dotted #aaa;"><!-- Template:RM top -->
:''The following is a closed discussion of a [[WP:requested moves|requested move]]. <span style="color:red">'''Please do not modify it.'''</span> Subsequent comments should be made in a new section on the talk page. Editors desiring to contest the closing decision should consider a [[Wikipedia:move review|move review]]. No further edits should be made to this section. ''
The result of the move request was: enacted as a technical request mirroring [[Reduced instruction set computer]] — [[User:Andy M. Wang|'''''Andy W.''''']] ([[User talk:Andy M. Wang|<span style="color:#164">talk</span>]]) 16:27, 24 May 2017 (UTC)
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[[:Complex instruction set computing]] → {{no redirect|Complex instruction set computer}} – For the same reasons as those presented at [[Talk:Reduced instruction set computing#Requested move 10 May 2017]]. [[User:50504F|50504F]] ([[User talk:50504F|talk]]) 04:26, 19 May 2017 (UTC)
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:''The above discussion is preserved as an archive of a [[Wikipedia:Requested moves|requested move]]. <span style="color:red">'''Please do not modify it.'''</span> Subsequent comments should be made in a new section on this talk page or in a [[Wikipedia:Move review|move review]]. No further edits should be made to this section.''</div><!-- Template:RM bottom -->
== Many dubious and unsourced claims ==
This article is mostly personal opinion and original research, rather than information from reliable sources. For example, the article equates RISC with load-store architecture, which doesn't match published RISC definitions. This ahistorical definition then leads to strange conclusions such as the Intel 4004 is a CISC. While it would be nice to have an easy definition where combining arithmetic and memory access = CISC, that's not the case. I could be [[WP:BOLD]] and delete all the uncited statements, but there wouldn't be much left, so I'm encouraging people to cite reliable sources. [[User:KenShirriff|KenShirriff]] ([[User talk:KenShirriff|talk]]) 02:39, 24 June 2023 (UTC)
:Is RISC ''currently'' being used in any technical sense other than "load/store architecture"? (It is often used as a ''marketing'' term, as in "CISC: tired; RISC: wired", but that's another matter.)
:"Doesn't use microcode" isn't that meaningful a definition of "RISC" any more. The [[Honeywell 6000]] series was hardwired but had some Pretty Complex Instructions, especially in machines with the EIS box, and the [[IBM System/360 Model 75]] was hardwired and implemented the full S/360 instruction set, complete with decimal arithmetic, ED/EDMK, TRT, etc. Furthermore, I'm not sure any current [[z/Architecture]] processors have anything that would be considered "microcode" - they have [[millicode]], but that is, as I understand it, closer to [[PALcode]], and apparently also have "i370"/"i390" code, which is somewhere above millicode but still used to implement some architectural features; both of them are subsets of z/Architecture machine code, with millicode being able to execute special chip-dependent instructions to peform certain functions. The [[Intel 80486]] executed some instructions directly in hardware; in the Pentium Pro and later, I have the impression that the microcode engine generates [[micro-operations]] that go into the same scheduler as the micro-operations generated by the instruction decoder.
:"All instructions take one clock tick" doesn't work any more unless you have not only a one-cycle combinatorial multiplier but a one-cycle combinatorial divider, given that many "RISC" instruction sets have integer multiply and divide and floating-point multiply and divide instructions.
:"Fixed-length instructions" may work better, but at least some architectures that are called "RISC" have compressed instructions (Thumb/Thumb-2/T2, whatever they're called in Power ISA, whatever RISC-V calls it).
:"No complex instructions" might work, but requires a definition of "complicated", and S/360, for example, may have had ED/EDMK (probably the most complicated instruction, both from the description and from the "is this just an attempt to turn some programming language construct into a single instruction?" notion), but its procedure call instructions BAL/BALR are rather close to the ones most RISC processors have (stuff next instruction PC into a register and jump; leave it up to whoever or whatever generates the code for the called instruction to decide what else to do). "No complex addressing modes" is similar, unless you consider double-indexing, present in both x86 and S/3x0, "too complex for RISC".
:And as for "CISC", as the article notes, it was coined retroactively, pretty much meaning "not RISC"; if "RISC" is interpreted sufficiently narrowly, "CISC" would then cover a rather wide range.
:So, yes, if there are widely-accepted (with sources to demonstrate the wide acceptance) definitions of RISC and CISC, that'd work, but, absent that, I'm not sure what could be done here. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 05:27, 24 June 2023 (UTC)
::And [https://dl.acm.org/doi/10.1145/641914.641917 Patterson and Ditzel's "The Case for the Reduced Instruction Set Computer"], which may have been the origin of the "RISC" and "CISC" terms, doesn't appear to offer firm definitions of ''either'' term. It offers individual examples of complexity, but no broad definition of "complexity" or reduction of same. (If somebody were to look at [[VAX]] and then at post-Advanced Function announcement [[IBM System/370|S/370]] (post-Advanced Function so they both have paged MMUs), and don't look at the S/370 I/O instructions, they might well conclude that the latter has less complexity than the former - much simpler procedure call instructions, fewer addressing modes and none that modify registers, and even simpler version of the decimal arithmetic/string processing/"this is for doing COBOL and PL/I PICTUREs" instructions.)
::So that paper could be considered a ''reliable'' source, but not a source very useful for the goal of clearly defining RISC or CISC.
::And the 6th edition of a book John Hennessy co-wrote with another researcher :-) doesn't, as I noted in [https://en.wikipedia.org/w/index.php?title=Complex_instruction_set_computer&diff=1161013939&oldid=1160988640 this edit], use the terms "RISC" or "CISC", so it may be more of a case of "RISC: tired, load-store architecture: wired" abd "CISC: tired, non-load-store architecture: wired" now. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 06:36, 24 June 2023 (UTC)
:::Yes, that's the point. RISC and CISC were vague terms in the 1980s and 1990s with multiple contradictory definitions. Since then, advances in computer architectures has made the terms less relevant and the definitions mostly meaningless.
:::As Steve Furber (co-designer of ARM) said in ''VLSI RISC Architecture and Organization'', "A Reduced Instruction Set Computer (RISC) is a member of an ill-defined class of computing machines. The common factor which associates members of the class is that they all have instruction sets which have been optimized more towards implementation efficiency than members of the alternative class of Complex Instruction Set Computers (CISCs), where the optimization is towards the minimization of the semantic gap between the instruction set and one or more high-level languages."
:::On the other hand, Blaau and Brooks say in ''Computer Architecture'', "An architecture in which most, if not all, operations can be implemented in a single datapath action and that has few constructs is called a reduced instruction-set computer (RISC). Early examples are STC ZEBRA, DEC PDP8, and first generation microprocessors such as the Intel 8008 and Motorola 6800."
:::And then you have the extremely quantitative definitions such as Tabak in ''RISC Architecture'':
:::1. Relatively low number of instructions, desirably less than 100
:::2. Low number of addressing modes, desirably 1 or 2
:::3. Low number of instruction formats, desirably 1 or 2, all of the same length
:::4. Single cycle execution of all instructions
:::5. Memory access performed by load/store only;
:::6. Relatively large register set, over 32, most operations register-to-register
:::7. Hardwired control unit (may be microprogrammed as technology develops)
:::8. Effort to support High Level Language operations
:::Thus, one has to accept that RISC and CISC never had nice, clean definitions and describe that with a [[WP:NPOV]] rather than trying to invent the One True Definition.
:::[[User:KenShirriff|KenShirriff]] ([[User talk:KenShirriff|talk]]) 18:03, 24 June 2023 (UTC)
::::BTW, [http://www.righto.com/2023/07/the-complex-history-of-intel-i960-risc.html your post on the 960] pointed to [https://yarchive.net/comp/risc_definition.html this sequence of John Mashey comp.arch posts], which is somewhat relevant here. Mashey seems to lean towards "CISC means 'not RISC'", and thinks talking about many older CPUs as "CISC" or "RISC" isn't a useful execise.
::::That's a sequence from 1992, from an era before the "throw a bunch of simple operations into a bucket and run them superscalar and out-of-order - which may involve chopping complex instructions into muliple simple operations" stuff, so it'd be interesting to see what he'd say now.
::::And the two CISC ISAs he seemed to put in the "relatively simple, as CISCs go" bucket 1) are the two remaining CISCs from that paper, 2) have a ton of money behind them (PC x86 processors and IBM mainframes), and 3) appear now to have implementations in the "throw a bunch of simple operations into a bucket and..." camp. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 22:53, 2 July 2023 (UTC)
== Combine CISC page with RISC? ==
I've been thinking that it would make sense to merge the CISC page into the RISC page. The problem is that the RISC and CISC page have a lot of overlap and mostly cover the same history and information, so they are largely redundant (when they aren't contradictory). As [[WP:OVERLAP]] says, "Remember, that Wikipedia is not a dictionary; there does not need to be a separate entry for every concept. For example, "flammable" and "non-flammable" can both be explained in an article on flammability."
I'm not saying that CISC is unimportant, of course. But since CISC is essentially defined in opposition to RISC, you can't really discuss one without the other. I think that combining the pages would improve both of them. Comments? [[User:KenShirriff|KenShirriff]] ([[User talk:KenShirriff|talk]]) 20:15, 4 December 2023 (UTC)
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