Talk:Inter-processor interrupt: Difference between revisions

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Revision as of 12:19, 14 June 2011 edit 134.191.232.68 (talk) →Cache coherency: new section ← Previous edit		Latest revision as of 23:01, 3 February 2024 edit undo Cewbot (talk \| contribs) Bots 8,374,032 edits m Maintain {{WPBS}} and vital articles: 1 WikiProject template. Create {{WPBS}}. Keep majority rating "Stub" in {{WPBS}}. Remove 1 same rating as {{WPBS}} in {{WikiProject Computing}}. Tag: Talk banner shell conversion
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Line 1: {{WikiProject ~~Computing~~banner shell\|class=Stub\| {{WikiProject Computing\|importance=\|hardware=yes\|auto=yes}} }} ==IPI vs IPC== I'm not sure whether it's really "IPI" instead of "IPC", but it makes much more sense! There are also much better hits under Google for "IPI interrupt" than for "IPC" Interrupt. Line 17 ⟶ 20: Current version says: "In x86 based systems, an IPI synchronizes the cache and memory management unit (MMU) between processors." I agree that IPI may be used on some systems for cache coherency, but x86 has (at least for several years) hardware cache coherency protocol (which is software-invisible and doesn't use IPI) <span style="font-size: smaller;" class="autosigned">— Preceding [[Wikipedia:Signatures\|unsigned]] comment added by [[Special:Contributions/134.191.232.68\|134.191.232.68]] ([[User talk:134.191.232.68\|talk]]) 12:19, 14 June 2011 (UTC)</span><!-- Template:UnsignedIP --> <!--Autosigned by SineBot-->