Content deleted Content added
link to more specific section, that discusses more specifically this topic. |
→References: +link |
||
| (2 intermediate revisions by 2 users not shown) | |||
Line 63:
<ref name="massoud">{{citation |url=http://sportlab.usc.edu/~massoud/Papers/isqed-tut.pdf |author-first1=Wei-Chung |author-last1=Cheng |author-first2=Massoud |author-last2=Pedram |title=Memory Bus Encoding for Low Power: A Tutorial}}</ref>
<ref name="Shifted_Gray">{{cite journal |author-first1=Hui |author-last1=Guo |author-first2=Sri |author-last2=Parameswaran |doi=10.1016/j.sysarc.2010.03.003 |volume=56 |issue=4–6 |date=April–June 2010 |title=Shifted Gray encoding to reduce instruction memory address bus switching for low-power embedded systems |journal=Journal of Systems Architecture |pages=180–190}}</ref>
<ref name="Zero-Transition_1997">{{cite journal |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=D. |author-last4=Sciuto |author4-link=Donatella Sciuto|author-first5=C. |author-last5=Silvano|author5-link=Cristina Silvano |title=Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems |journal=Proceedings Seventh Great Lakes Symposium on VLSI |pages=77–82 |date=March 1997}}</ref>
<ref name="Stan_1995">{{cite journal |author-first1=Mircea R. |author-last1=Stan |author-first2=Wayne P. |author-last2=Burleson |title=Bus-Invert Coding for Low-Power I/O |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=3 |number=1 |pages=49–58 |date=March 1995 |id=1063-8210/95$04.00 |citeseerx=10.1.1.89.2154 |doi=10.1109/92.365453 }}</ref>
<ref name="Inversion">{{cite web |url=http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt}}</ref>
<ref name="Yang">{{cite journal |author-first1=J. |author-last1=Yang |display-authors=et al |title=FV encoding for low power data I/O |journal=Islped 2001 |date=August 2001 |pages=84–87}}</ref>
<ref name="Basu">{{cite journal |author-last1=Basu |display-authors=et al |title=Power protocol: reducing power dissipation on off-chip data buses |journal=
<ref name="Lin">{{cite journal |author-first1=C.-H. |author-last1=Lin |display-authors=et al |title=Hierarchical Value Cache Encoding for Off-Chip Data Bus |journal=ISLPED |date=2006}}</ref>
<ref name="Sector">{{cite web |url=http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf |title=Transition Reduction in Memory Buses Using Sector-based Encoding Techniques |author-first1=Yazdan |author-last1=Aghaghiri |author-first2=Farzan |author-last2=Fallah |author-first3=Massoud |author-last3=Pedram}}</ref>
<ref name="Deogun">{{cite journal |author-first1=H. |author-last1=Deogun |author-first2=R. |author-last2=Rao |author-first3=D. |author-last3=Sylvester |author-first4=D. |author-last4=Blaauw |author-link4=D. Blaauw |title=Leakage- and crosstalk-aware bus encoding for total power reduction |journal=Proceedings of the 41st Design Automation Conference |pages=779–782 |date=June 2004}}</ref>
<ref name="Khan">{{cite journal |author-first1=Z. |author-last1=Khan |author-first2=T. |author-last2=Arslan |author-first3=A. |author-last3=Erdogan |title=A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems |journal=Proceedings of the 18th International Conference on VLSI Design |pages=751–756 |date=January 2005}}</ref>
<ref name="VLSI">{{cite journal |url=http://si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf |title=Power Optimization of Core-Based Systems by Address Bus Encoding |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=Massimo |author-last4=Poncino |author-first5=Stefano |author-last5=Quer |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=6 |number=4 |date=December 1998}}</ref>
| |||