Bus encoding: Difference between revisions

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'''Bus encoding''' refers to converting/encoding a piece of data to another form before launching on the [[bus (computing)|bus]]. While bus encoding can be used to serve various purposes like reducing the number of pins, compressing the data to be transmitted, reducing cross-talk between bit lines, etc., it is one of the popular techniques used in system design to reduce dynamic power consumed by the [[system bus]].<ref>[http://sportlab.usc.edu/~massoud/Papers/low-power-RTL-review-journal.pdf M. Pedram and A Abdollahi, name="Low Power RT-Level Synthesis Techniques: A TutorialRTL"]</ref><ref name="devdasmalik">Devadas & Malik, "A Survey of Optimization Techniques targeting Low Power VLSI Circuits", DAC 32, 1995, pp. 242-247</ref> Bus encoding aims to reduce the [[hammingHamming distance]] between 2 consecutive values on the bus. Since the activity is directly proportional to the hamming[[Hamming distance]], bus encoding proves to be effective in reducing the overall activity factor thereby reducing the dynamic power consumption in the system.

In the context of this article, a system can refer to anything where data is transferred from one element to another over bus (viz. [[System on a Chip]] (SoC), a computer system, an [[embedded system]] on board, etc.).

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# ''Power dissipation'': As per the [[Moore's law]], semiconductor devices have been packing more and more transistors in smaller amount of area. This leads to higher power dissipation per unit area and makes packaging and thermal cooling system design complex and costly. Hence, low power electronic systems are needed to tackle this issue.

The dynamic power dissipated by an electronic circuit is directly proportional to the activity factor and the load capacitance as seen by the output of the logic gate. In case of a bus, the load capacitance is usually high since bus needs to be connected to multiple modules and routed longer and the activity factor is also high. Due to higher value of load capacitance and activity factor, in a typical system, bus power consumption can contribute up to 50% of the total power consumption. Bus encoding aims to reduce this power by reducing the amount of activity (number of toggles) in the bus lines. While the kind of bus encoding to be used for a particular system can be best determined when the target application and environmental constraints about the system are known apriori, described below are some bus encoding techniques which can help reduce bus power for most systems. Hence bus encoding is important for any electronic system design.

Hence bus encoding is important for any electronic system design.{{Citation needed|reason=most electronic systems use only microcontrollers or no processor at all, and my understanding is that they don't implement any bus encoding, therefore "any electronic system" is overstating its importance.|date=July 2019}}

== Examples of bus encoding to achieve low power==

Following are some of the implementations to use Busbus Encodingencoding for reducing dynamic power consumption in different scenarios:

# ''[[Gray encodingcode addressing]]'':<ref name="massoud">[http://sportlab.usc.edu/~massoud/Papers/isqed-tut.pdf Wei-Chung Cheng and Massoud Pedram "Memory Bus Encoding for Low Power: A Tutorial"]</ref> The address lines of a bus in most of the computing systems increase in consecutive numerical values due to [[Locality of reference|spatial locality]]. If we use regular binary coding for the bus, we are not assured of minimal hammingHamming distance between 2 consecutive addresses. Using grayGray codes for encoding the address lines will lead to a hammingHamming distance of 1 between any 2 consecutive address bus values (as long as spatial locality holds). There are variations to this scheme named Shifted grayGray encoding to reduce the delay overhead.<ref>{{cite journal | url name= http:"Shifted_Gray"//www.sciencedirect.com/science/article/pii/S1383762110000159 | doi=10.1016/j.sysarc.2010.03.003 | volume=56 | title=Shifted gray encoding to reduce instruction memory address bus switching for low-power embedded systems | journal=Journal of Systems Architecture | pages=180–190}}</ref>

# ''Sequential addressing or T0 codes'':<ref>L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, name="Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based SystemsTransition_1997", Proceedings Seventh Great Lakes Symposium on VLSI, pp. 77-82, March 1997.</ref> In case of address bus, due to spatial locality that exists in programs, most of the transitions involve changing the address to the next consecutive value. A possible encoding scheme is to use an additional line, INC, in the bus indicating whether the current transition is the next increment address or not. If it is not a consecutive address, then the receiver can use the value on the bus. But if it is a consecutive address, the transmitter need not change the value in the bus, but just assert the INC line to 1. In such case, for a continuous addressing scheme, there is no transition at all on the bus, leading to a bus activity factor of 0.

# ''Number representation'': Let us considerConsider an example of a system which gets one of its data from a sensor. Most of the times, the sensor may be measuring some noise and for this example, let us consider that the values being measured are (0) and (-1) alternatively. For a 32-bit data bus, value 0 translates to 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) while (-1) translates to 0xFFFFFFFF (1111 1111 1111 1111 1111 1111 1111 1111) in a 2’s complement representation. We see that the hammingHamming distance in this case is 32 (since all 32-bits are changing their state). Instead, if we encode the bus to use signed integer representation (MSB is sign bit), we can represent 0 as 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) and -1 as 0x80000001 (1000 0000 0000 0000 0000 0000 0000 0001) . In this case, we see that the hammingHamming distance between the numbers is just 2. Hence by using a 2’s complement to signed arithmetic encoding, we are able to reduce the activity from a factor of 32 to 2.

# ''[[Inversion encoding]]'':<ref>M. R. Stan and W. P. Burleson, name="Bus-invert coding for low-power I/OStan_1995", IEEE Transactions On VLSI Systems, Vol. 3, No. 1, pp. 49-58, 1995</ref><ref>http: name="Inversion"//www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt</ref> This is another implementation of bus encoding where an additional line named INV is added to the bus lines. Depending on the value of the INV line, the other lines will be used with or without inversion. e.g. if INV line is 0, the data on the bus is sampled as it is but if INV line is 1, the data on the bus is inverted before any processing on it. Referring to the example used in 3, instead of using a signed integer representation, we could continue using 2’s complement and achieve the same activity reduction using inversion encoding. So, 0 will be represented as 0x00000000 with INV=0 and -1 will be represented as 0x00000000 with INV=1. Since INV=1, receiver will invert the data before consuming it, thereby converting it to 0xFFFFFFFF internally. In this case, only 1 bit (INV bit) is changed over bus leading to an activity of factor 1. In general, in inversion encoding, the encoder computes the hammingHamming distance between the current value and next value and based on that, determines whether to use INV=0 or INV=1.

# ''[[Value cache encoding]]'':<ref>J. name="Yang et. al, "FV encoding for low power data I/O", ISLPED 2001, August 2001, pp. 84-87</ref> This is another form of Bus encoding, primarily used for external (off-chip) Busses. A [[associative array | dictionary]] (value cache) is maintained at both the sender and receiver end about some of the commonly shared data patterns. Instead of passing the data patterns each time, the sender just toggles one bit indicating which entry from value cache to be used at the receiver end. Only for values which are not present in the value cache, the complete data is sent over the bus. There has been various modified implementations of this technique with an intent to maximize the hits for the value cache, but the underlying idea is the same.<ref>Basu et.al., name="Power protocol: reducing power dissipation on off-chip data busesBasu", MICRO 2002</ref><ref>C-H name="Lin et.al., Hierarchical Value Cache Encoding for Off-Chip Data Bus, ISLPED 2006<"/ref>

# ''Other techniques'' like sector-based encoding,<ref>http: name="Sector"//sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf</ref> variations of inversion coding, have also been proposed. There has been work on using bus encodings which lower the leakage power consumption as well along with reducing the crosstalk with minimal impact on path delays.<ref>H. name="Deogun, R. R. Rao, D. Sylvester, and D. Blaauw. Leakage- and crosstalk-aware bus encoding for total power reduction. In Proceedings of the 41st Design Automation Conference, pages 779–782, June 2004.<"/ref><ref>Z. name="Khan, T. Arslan, and A. Erdogan. A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems. In Proceedings of the 18th International Conference on VLSI Design, pages 751–756. IEEE Computer Society, January 2005.<"/ref>

== Other examples of bus encoding ==

Many other types of bus encoding have been developed for a variety of reasons:

* improved EMC: [[differential signaling]] used in many buses, and the more general [[constant-weight code]] used in the MIPI C-PHY [[Camera Serial Interface]]<ref>

[https://www.design-reuse.com/articles/43954/demystifying-mipi-c-phy-dphy-subsystem.html "Demystifying MIPI C-PHY / DPHY Subsystem - Tradeoffs, Challenges, and Adoption"]

([https://www.chipestimate.com/Demystifying-MIPI-C-PHY--DPHY-Subsystem-Tradeoffs-Challenges-and-Adoption-/Mixel/Technical-Article/2018/04/24 mirror])

</ref> are both more immune to outside interference, and emit less interference to other devices.

* bus multiplexing: Many early microprocessors and many early DRAM chips reduced costs by using bus multiplexing, rather than dedicate a pin to every address bit and data bit of the [[system bus]]. One approach re-uses the address bus pins at different times for data bus pins,<ref>

Don Lancaster.

[https://www.tinaja.com/ebooks/tvtcb.pdf "TV Typewriter Cookbook"]. ([[TV Typewriter]]).

Section "Bus Organization".

p. 82.

</ref> an approach used by [[conventional PCI]]. Another approach re-uses the same pins at different times for the upper half and for the lower half of the address bus, an approach used by many [[dynamic random-access memory]] chips, adding 2 pins to the control bus -- a row-address strobe ({{overline|RAS}}) and the column-address strobe ({{overline|CAS}}).

== Implementation method ==

In case of SoC designs, bus encoding schemes can be best implemented in RTL by instantiating dedicated encoders and decoders over the bus. Another way it could be implemented is by passing hint to the synthesis tool either as a trace of the simulation<ref>http: name="VLSI"//si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf</ref> or by using synthesis pragma to define the type of encoding needed.

On board, a small low power IC can be deployed in between the master and slave modules on the bus to implement the encoding and decoding functions.

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== See also ==

* [[Gray code addressing]]

* [[CPU power dissipation|Power dissipation]]

* [[Low power electronics]]

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==References==

{{Reflist|refs=

{{reflist}}

<ref name="RTL">{{citation |url=http://sportlab.usc.edu/~massoud/Papers/low-power-RTL-review-journal.pdf |author-first1=Massoud |author-last1=Pedram |author-first2=A. |author-last2=Abdollahi |title=Low Power RT-Level Synthesis Techniques: A Tutorial}}</ref>

<ref name="devdasmalik">{{citation |author-last1=Devadas |author-last2=Malik |title=A Survey of Optimization Techniques targeting Low Power VLSI Circuits |journal=DAC 32 |date=1995 |pages=242–247}}</ref>

<ref name="massoud">{{citation |url=http://sportlab.usc.edu/~massoud/Papers/isqed-tut.pdf |author-first1=Wei-Chung |author-last1=Cheng |author-first2=Massoud |author-last2=Pedram |title=Memory Bus Encoding for Low Power: A Tutorial}}</ref>

<ref name="Shifted_Gray">{{cite journal |author-first1=Hui |author-last1=Guo |author-first2=Sri |author-last2=Parameswaran |doi=10.1016/j.sysarc.2010.03.003 |volume=56 |issue=4–6 |date=April–June 2010 |title=Shifted Gray encoding to reduce instruction memory address bus switching for low-power embedded systems |journal=Journal of Systems Architecture |pages=180–190}}</ref>

<ref name="Zero-Transition_1997">{{cite journal |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=D. |author-last4=Sciuto |author4-link=Donatella Sciuto|author-first5=C. |author-last5=Silvano|author5-link=Cristina Silvano |title=Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems |journal=Proceedings Seventh Great Lakes Symposium on VLSI |pages=77–82 |date=March 1997}}</ref>

<ref name="Stan_1995">{{cite journal |author-first1=Mircea R. |author-last1=Stan |author-first2=Wayne P. |author-last2=Burleson |title=Bus-Invert Coding for Low-Power I/O |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=3 |number=1 |pages=49–58 |date=March 1995 |id=1063-8210/95$04.00 |citeseerx=10.1.1.89.2154 |doi=10.1109/92.365453 }}</ref>

<ref name="Inversion">{{cite web |url=http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt}}</ref>

<ref name="Yang">{{cite journal |author-first1=J. |author-last1=Yang |display-authors=et al |title=FV encoding for low power data I/O |journal=Islped 2001 |date=August 2001 |pages=84–87}}</ref>

<ref name="Basu">{{cite journal |author-last1=Basu |display-authors=et al |title=Power protocol: reducing power dissipation on off-chip data buses |journal=Micro |date=2002}}</ref>

<ref name="Lin">{{cite journal |author-first1=C.-H. |author-last1=Lin |display-authors=et al |title=Hierarchical Value Cache Encoding for Off-Chip Data Bus |journal=ISLPED |date=2006}}</ref>

<ref name="Sector">{{cite web |url=http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf |title=Transition Reduction in Memory Buses Using Sector-based Encoding Techniques |author-first1=Yazdan |author-last1=Aghaghiri |author-first2=Farzan |author-last2=Fallah |author-first3=Massoud |author-last3=Pedram}}</ref>

<ref name="Deogun">{{cite journal |author-first1=H. |author-last1=Deogun |author-first2=R. |author-last2=Rao |author-first3=D. |author-last3=Sylvester |author-first4=D. |author-last4=Blaauw |author-link4=D. Blaauw |title=Leakage- and crosstalk-aware bus encoding for total power reduction |journal=Proceedings of the 41st Design Automation Conference |pages=779–782 |date=June 2004}}</ref>

<ref name="Khan">{{cite journal |author-first1=Z. |author-last1=Khan |author-first2=T. |author-last2=Arslan |author-first3=A. |author-last3=Erdogan |title=A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems |journal=Proceedings of the 18th International Conference on VLSI Design |pages=751–756 |date=January 2005}}</ref>

<ref name="VLSI">{{cite journal |url=http://si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf |title=Power Optimization of Core-Based Systems by Address Bus Encoding |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=Massimo |author-last4=Poncino |author-first5=Stefano |author-last5=Quer |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=6 |number=4 |date=December 1998}}</ref>

}}

==Further reading==

* {{cite report |author-first1=Ching-Long |author-last1=Su |author-first2=Chi-Ying |author-last2=Tsui |author-first3=Alvin M. |author-last3=Despain |url=http://www.scarpaz.com/2100-papers/Power%20Estimation/su94-low%20power%20architecture%20and%20compilation.pdf |title=Low Power Architecture Design and Compilation Techniques for High-Performance Processors |date=1994 |publisher=Advanced Computer Architecture Laboratory |id=ACAL-TR-94-01}}

[[Category:Digital electronics]]