Bus encoding: Difference between revisions

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== Examples of bus encoding to achieve low power==

Following are some of the implementations to use bus encoding for reducing dynamic power consumption in different scenarios:

# ''[[Gray encodingcode addressing]]'':<ref name="massoud"/> The address lines of a bus in most of the computing systems increase in consecutive numerical values due to [[Locality of reference|spatial locality]]. If we use regular binary coding for the bus, we are not assured of minimal Hamming distance between 2 consecutive addresses. Using Gray codes for encoding the address lines will lead to a Hamming distance of 1 between any 2 consecutive address bus values (as long as spatial locality holds). There are variations to this scheme named Shifted Gray encoding to reduce the delay overhead.<ref name="Shifted_Gray"/>

# ''Sequential addressing or T0 codes'':<ref name="Zero-Transition_1997"/> In case of address bus, due to spatial locality that exists in programs, most of the transitions involve changing the address to the next consecutive value. A possible encoding scheme is to use an additional line, INC, in the bus indicating whether the current transition is the next increment address or not. If it is not a consecutive address, then the receiver can use the value on the bus. But if it is a consecutive address, the transmitter need not change the value in the bus, but just assert the INC line to 1. In such case, for a continuous addressing scheme, there is no transition at all on the bus, leading to a bus activity factor of 0.

# ''Number representation'': Consider an example of a system which gets one of its data from a sensor. Most of the times, the sensor may be measuring some noise and for this example, consider that the values being measured are (0) and (-1) alternatively. For a 32-bit data bus, value 0 translates to 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) while (-1) translates to 0xFFFFFFFF (1111 1111 1111 1111 1111 1111 1111 1111) in a 2’s complement representation. We see that the Hamming distance in this case is 32 (since all 32-bits are changing their state). Instead, if we encode the bus to use signed integer representation (MSB is sign bit), we can represent 0 as 0x00000000 (0000 0000 0000 0000 0000 0000 0000 0000) and -1 as 0x80000001 (1000 0000 0000 0000 0000 0000 0000 0001) . In this case, we see that the Hamming distance between the numbers is just 2. Hence by using a 2’s complement to signed arithmetic encoding, we are able to reduce the activity from a factor of 32 to 2.

# ''[[Inversion encoding]]'':<ref name="Stan_1995"/><ref name="Inversion"/> This is another implementation of bus encoding where an additional line named INV is added to the bus lines. Depending on the value of the INV line, the other lines will be used with or without inversion. e.g. if INV line is 0, the data on the bus is sampled as it is but if INV line is 1, the data on the bus is inverted before any processing on it. Referring to the example used in 3, instead of using a signed integer representation, we could continue using 2’s complement and achieve the same activity reduction using inversion encoding. So, 0 will be represented as 0x00000000 with INV=0 and -1 will be represented as 0x00000000 with INV=1. Since INV=1, receiver will invert the data before consuming it, thereby converting it to 0xFFFFFFFF internally. In this case, only 1 bit (INV bit) is changed over bus leading to an activity of factor 1. In general, in inversion encoding, the encoder computes the Hamming distance between the current value and next value and based on that, determines whether to use INV=0 or INV=1.

# ''[[Value cache encoding]]'':<ref name="Yang"/> This is another form of Bus encoding, primarily used for external (off-chip) Busses. A [[associative array | dictionary]] (value cache) is maintained at both the sender and receiver end about some of the commonly shared data patterns. Instead of passing the data patterns each time, the sender just toggles one bit indicating which entry from value cache to be used at the receiver end. Only for values which are not present in the value cache, the complete data is sent over the bus. There has been various modified implementations of this technique with an intent to maximize the hits for the value cache, but the underlying idea is the same.<ref name="Basu"/><ref name="Lin"/>

# ''Other techniques'' like sector-based encoding,<ref name="Sector"/> variations of inversion coding, have also been proposed. There has been work on using bus encodings which lower the leakage power consumption as well along with reducing the crosstalk with minimal impact on path delays.<ref name="Deogun"/><ref name="Khan"/>

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([https://www.chipestimate.com/Demystifying-MIPI-C-PHY--DPHY-Subsystem-Tradeoffs-Challenges-and-Adoption-/Mixel/Technical-Article/2018/04/24 mirror])

</ref> are both more immune to outside interference, and emit less interference to other devices.

* bus multiplexing: Many early microprocessors and many early DRAM chips reduced costs by using bus multiplexing, rather than dedicate a pin to every address bit and data bit of the [[system bus]]. One approach re-uses the address bus pins at different times for data bus pins,<ref>
Don Lancaster.
[https://www.tinaja.com/ebooks/tvtcb.pdf "TV Typewriter Cookbook"]. ([[TV Typewriter]]).
Section "Bus Organization".
p. 82.
</ref> an approach used by [[conventional PCI]]. Another approach re-uses the same pins at different times for the upper half and for the lower half of the address bus, an approach used by many [[dynamic random-access memory]] chips, adding 2 pins to the control bus -- a row-address strobe ({{overline|RAS}}) and the column-address strobe ({{overline|CAS}}).

== Implementation method ==

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<ref name="massoud">{{citation |url=http://sportlab.usc.edu/~massoud/Papers/isqed-tut.pdf |author-first1=Wei-Chung |author-last1=Cheng |author-first2=Massoud |author-last2=Pedram |title=Memory Bus Encoding for Low Power: A Tutorial}}</ref>

<ref name="Shifted_Gray">{{cite journal |author-first1=Hui |author-last1=Guo |author-first2=Sri |author-last2=Parameswaran |doi=10.1016/j.sysarc.2010.03.003 |volume=56 |issue=4–6 |date=April–June 2010 |title=Shifted Gray encoding to reduce instruction memory address bus switching for low-power embedded systems |journal=Journal of Systems Architecture |pages=180–190}}</ref>

<ref name="Zero-Transition_1997">{{cite journal |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=D. |author-last4=Sciuto |author4-link=Donatella Sciuto|author-first5=C. |author-last5=Silvano|author5-link=Cristina Silvano |title=Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems |journal=Proceedings Seventh Great Lakes Symposium on VLSI |pages=77–82 |date=March 1997}}</ref>

<ref name="Stan_1995">{{cite journal |author-first1=Mircea R. |author-last1=Stan |author-first2=Wayne P. |author-last2=Burleson |title=Bus-Invert Coding for Low-Power I/O |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=3 |number=1 |pages=49–58 |date=March 1995 |id=1063-8210/95$04.00 |citeseerx=10.1.1.89.2154 |doi=10.1109/92.365453 }}</ref>

<ref name="Inversion">{{cite web |url=http://www.eng.auburn.edu/~agrawvd/COURSE/E6270_Fall07/PROJECT/JIANG/Low%20power%2032-bit%20bus%20with%20inversion%20encoding.ppt}}</ref>

<ref name="Yang">{{cite journal |author-first1=J. |author-last1=Yang |display-authors=et al |title=FV encoding for low power data I/O |journal=Islped 2001 |date=August 2001 |pages=84–87}}</ref>

<ref name="Basu">{{cite journal |author-last1=Basu |display-authors=et al |title=Power protocol: reducing power dissipation on off-chip data buses |journal=MICROMicro |date=2002}}</ref>

<ref name="Lin">{{cite journal |author-first1=C.-H. |author-last1=Lin |display-authors=et al |title=Hierarchical Value Cache Encoding for Off-Chip Data Bus |journal=ISLPED |date=2006}}</ref>

<ref name="Sector">{{cite web |url=http://sportlab.usc.edu/~massoud/Papers/sector-based-encoding-journal.pdf |title=Transition Reduction in Memory Buses Using Sector-based Encoding Techniques |author-first1=Yazdan |author-last1=Aghaghiri |author-first2=Farzan |author-last2=Fallah |author-first3=Massoud |author-last3=Pedram}}</ref>

<ref name="Deogun">{{cite journal |author-first1=H. |author-last1=Deogun |author-first2=R. |author-last2=Rao |author-first3=D. |author-last3=Sylvester |author-first4=D. |author-last4=Blaauw |author-link4=D. Blaauw |title=Leakage- and crosstalk-aware bus encoding for total power reduction |journal=Proceedings of the 41st Design Automation Conference |pages=779–782 |date=June 2004}}</ref>

<ref name="Khan">{{cite journal |author-first1=Z. |author-last1=Khan |author-first2=T. |author-last2=Arslan |author-first3=A. |author-last3=Erdogan |title=A novel bus encoding scheme from energy and crosstalk efficiency perspective for AMBA based generic SoC systems |journal=Proceedings of the 18th International Conference on VLSI Design |pages=751–756 |date=January 2005}}</ref>

<ref name="VLSI">{{cite journal |url=http://si2.epfl.ch/~demichel/publications/archive/1998/VLSISvol4iss4Dec98pg554.pdf |title=Power Optimization of Core-Based Systems by Address Bus Encoding |author-first1=Luca |author-last1=Benini |author-first2=Giovanni |author-last2=De Micheli |author-first3=Enrico |author-last3=Macii |author-first4=Massimo |author-last4=Poncino |author-first5=Stefano |author-last5=Quer |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=6 |number=4 |date=December 1998}}</ref>