Open Verification Methodology: Difference between revisions

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The '''Open Verification Methodology''' (OVM) is a documented [[methodology]] with a supporting building-block library for the verification of semiconductor chip designs. The initial version, OVM 1.0, was released in January, 2008,<ref>[http://www.ovmworld.org/press_release_010908.php OVM 1.0 Announcement]</ref> and regular updates have expanded its functionality. The latest version is OVM 2.1.2, released in January, 2011.

The reuse concepts within the OVM were derived mainly from the URM (Universal Reuse Methodology (URM) which was, to a large part, based on the [[ERM (e Reuse Methodology)|eRM]] (e Reuse MethodologyERM) for the [[e (verification language)|e Verification Language]] developed by Verisity Design in 2001. The OVM also brings in concepts from the Advanced Verification Methodology (AVM). The [[Universal Verification Methodology|UVM]] class library brings much automation to the [[SystemVerilog]] language such as sequences and data automation features (packing, copy, compare), etc.). The UVM also has recommendations for code packaging and naming conventions.

==References==

<!--- See [[Wikipedia:Footnotes]] on how to create references using <ref></ref> tags which will then appear here automatically -->

{{Reflist}}

*[http://www.accellera.org/activities/vip/VIP-TC_standard_effort_update_Jan_2010.pdf OVM Relationship to the UVM]

==External Linkslinks==

* [http://www.edaplayground.com EDA Playground] - run OVM simulations from a web browser (free online IDE)

*[http://www.accellera.org/activities/vip/VIP-TC_standard_effort_update_Jan_2010.pdf OVM Relationship to the UVM]

[[Category:Electronic design automation]]