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{{Use dmy dates|date=August 2019|cs1-dates=y}}
'''Inversion
== Overview ==
The
* High capacitance lines
* High switching
#
# If the Hamming distance is larger than n/2,
# Otherwise
# At the receiver side the contents of the bus must be conditionally inverted according to the invert line, unless the data is not stored encoded as it is (e.g., in a RAM). In any case, the
== Example ==
[[File:Overviewbusencoding.png|thumb|Overview for Performance Analysis: inversion encoding]]
== Performance Analysis ==▼
The
While the maximum
In order to decrease the average I/O power dissipation for wide buses the observation that the
== See also ==
▲== Partitioned Inversion Encoding ==
* [[Bus encoding]]
* [[Two's complement]]
* [[Low-power electronics]]
* [[CPU power dissipation]]
== References ==
▲In order to decrease the average I/O power dissipation for wide buses the observation that the Bus-Invert method performs better for small n can be used to partition the bus into several narrower subbuses. Each of these subbuses can then be coded independently with its own invert signal. For example a 64-bit bus could be partitioned into eight 8-bit subbuses with a total of eight n order to decrease the average I/O power dissipation for wide buses the observation that the Bus-Invert method performs better for small n can be used to partition the bus into several narrower subbuses. Each of these subbuses can then be coded independently with its own invert signal. For example a 64-bit bus could be partitioned into eight 8-bit subbuses with a total of eight invert signals. Because of the assumption that the data to be transferred over the wide bus is random uniformly distributed, the statistics for the narrower subbuses will be independent and the sequence of data for each subbus will be random uniformly distributed. For example for a 64-bit bus partitioned into eight 8-bit subbuses the average number of transitions per time-slot will be 26.16 (8 times 3.27, the average for one 8-bit subbus) and the average number of transitions per bus-line per time-slot will be .41 (as for an 8-bit bus with one invert line). The maximum number of transitions is not improved by partitioning the bus and remains the same n/2. However, there is always an extra overhead of using more lines, but computationally, it has been found that the inversion bus encoding works well for most purposes.
{{Reflist|refs=
<ref name="Stan_1995">{{cite journal |author-first1=Mircea R. |author-last1=Stan |author-first2=Wayne P. |author-last2=Burleson |title=Bus-Invert Coding for Low-Power I/O |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=3 |number=1 |pages=49–58 |date=March 1995 |id=1063-8210/95$04.00 |citeseerx=10.1.1.89.2154 |doi=10.1109/92.365453 }}</ref>
}}
==Further reading==
* {{cite book |author-first=Vincent C. |author-last=Gaudet |chapter=Chapter 4.1. Low-Power Design Techniques for State-of-the-Art CMOS Technologies |editor-first=Bernd |editor-last=Steinbach |editor-link=:de:Bernd Steinbach |title=Recent Progress in the Boolean Domain |publisher=[[Cambridge Scholars Publishing]] |publication-place=Newcastle upon Tyne, UK |___location=Freiberg, Germany |edition=1 |date=2014-04-01 |orig-date=2013-09-25 |isbn=978-1-4438-5638-6 |pages=187–212 |url=https://books.google.com/books?id=_pwxBwAAQBAJ |access-date=2019-08-04}} [https://web.archive.org/web/20210228020207/https://www.tau.ac.il/~ilia1/publications/rpbd_book.pdf<!-- https://m.tau.ac.il/~ilia1/publications/rpbd_book.pdf draft version 2013-09-25 -->] (xxx+428 pages)
[[Category:Electronics optimization]]
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