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{{Use dmy dates|date=August 2019|cs1-dates=y}}
'''Inversion
== Overview ==
The
=== Usage
* High capacitance lines
* High switching
=== Bus-
#
# If the Hamming distance is larger than n/2,
# Otherwise
# At the receiver side the contents of the bus must be conditionally inverted according to the invert line, unless the data is not stored encoded as it is (e.g., in a RAM). In any case, the
== Example ==
[[File:Overviewbusencoding.png|thumb|Overview for Performance Analysis: inversion encoding]]
== Performance
The bus-invert method generates a code that has the property that the maximum number of transitions per time-slot is reduced from n to n/2+1 and thus the peak power dissipation for [[input/output]] (I/O) is reduced by nearly the half. From the [[coding theory]] point of view, the bus-invert code is a time-dependent Markovian code.
While the maximum number of transitions is reduced by half, the average number has a smaller decrease. For an 8-bit bus for example, the average number of transitions, using bus-invert coding becomes 3.27 (instead of 4), or 0.41 (instead of 0.5) transitions per bus-line per time-slot. This means that the average number of transitions is 81.8% of the number with an unencoded bus. This is because the invert line contributes some transitions and the distribution of the Hamming distances is not uniform.<ref
== Partitioned
In order to decrease the average I/O power dissipation for wide buses the observation that the
== See also ==
* [[Bus
* [[Two's
* [[Low-power electronics]]
* [[CPU power dissipation
== References ==
{{Reflist
<ref name="Stan_1995">{{cite journal |author-first1=Mircea R. |author-last1=Stan |author-first2=Wayne P. |author-last2=Burleson |title=Bus-Invert Coding for Low-Power I/O |journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems |volume=3 |number=1 |pages=49–58 |date=March 1995 |id=1063-8210/95$04.00 |citeseerx=10.1.1.89.2154 |doi=10.1109/92.365453 }}</ref>
}}
==Further reading==
* {{cite book |author-first=Vincent C. |author-last=Gaudet |chapter=Chapter 4.1. Low-Power Design Techniques for State-of-the-Art CMOS Technologies |editor-first=Bernd |editor-last=Steinbach |editor-link=:de:Bernd Steinbach |title=Recent Progress in the Boolean Domain |publisher=[[Cambridge Scholars Publishing]] |publication-place=Newcastle upon Tyne, UK |___location=Freiberg, Germany |edition=1 |date=2014-04-01 |orig-date=2013-09-25 |isbn=978-1-4438-5638-6 |pages=187–212 |url=https://books.google.com/books?id=_pwxBwAAQBAJ |access-date=2019-08-04}} [https://web.archive.org/web/20210228020207/https://www.tau.ac.il/~ilia1/publications/rpbd_book.pdf<!-- https://m.tau.ac.il/~ilia1/publications/rpbd_book.pdf draft version 2013-09-25 -->] (xxx+428 pages)
[[Category:Electronics optimization]]
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