Power Processing Element: Difference between revisions

Revision as of 12:46, 4 February 2014

Latest revision as of 02:43, 7 September 2024

(45 intermediate revisions by 26 users not shown)

Line 1:

{{Short description|In microprocessor architecture}}

{{refimprove|date=February 2014}}

{{Redirect|Power Processing Unit|the electrical circuit device|Power processing unit}}

The '''Power Processing Element''' is a [[microprocessor]] designed by [[IBM]] for use primarily in the [[game console]]s [[Playstation 3]] and [[Xbox 360]]. It is a 64-bit, dual-threaded, [[PowerPC]] architecture.

{{More citations needed|date=April 2020}}

{{POWER, PowerPC, and Power ISA}}

{{Infobox CPU

| name = Power Processing Element

| image =

| image_size =

| caption =

| produced-start = 2005

| produced-end = Present

| slowest = 2.8 | slow-unit = GHz

| fastest = 3.2 | fast-unit = GHz

| size-from = 90 nm

| size-to = 45 nm

| soldby = [[IBM]], [[Sony]], [[Microsoft]]

| designfirm = [[IBM]]

| manuf1 = [[IBM]]

| arch = [[PowerPC 2.02]]

| microarch = PPU

| code =

| numcores = 1

| l1cache = 32 KB instruction + 32 KB data

| l2cache =

| l3cache =

| gpu = [[Xenos (graphics chip)|Xenos]], in the [[Xenon (processor)#XCGPU|XCGPU]] variant.

| application = [[Video game console|Gaming Console]], [[High Performance Computing|HPC]]

| predecessor =

| successor = [[IBM A2]]

| variant = [[Cell (microprocessor)|Cell BE]], [[Xenon (processor)|XCPU]], [[Xenon (processor)#XCGPU|XCGPU]], [[Cell processor#PowerXCell 8i|PowerXCell 8i]]

}}

The '''Power Processing Element''' ('''PPE''') comprises a '''Power Processing Unit''' ('''PPU''') and a 512 KB L2 cache. In most instances the PPU is used in a PPE. The PPU is a [[64-bit]] [[multithreading (computer architecture)|dual-threaded]] [[Out-of-order execution|in-order]] [[PowerPC 2.02]] [[microprocessor]] [[multi-core processor|core]] designed by [[IBM]] for use primarily in the [[game console]]s [[PlayStation 3]] and [[Xbox 360]], but has also found applications in high performance computing in [[supercomputer]]s such as the record setting [[IBM Roadrunner]].

The PPU is used as a main CPU core in three different processor designs:

* The [[Cell (microprocessor)|Cell Broadband Engine]] (Cell BE) which is used primarily in [[Sony]]'s [[PlayStation 3]] gaming console. It uses the PPE and comes in three versions, a 90 nm, a 65 nm and a 45 nm part.

* The [[Cell (microprocessor)#PowerXCell 8i|PowerXCell 8i]] which is a version of the Cell BE with enhanced FPU and memory subsystem. It was only manufactured as a single 65 nm version.

* The [[Xenon (processor)|XCPU]] which is used in a three-core configuration and a unified 1 MB L2 cache inside Microsoft's [[Xbox 360]]. It comes in three versions, the 90 nm and 65 nm versions, and the 45 nm [[Xenon (processor)#XCGPU|XCGPU]] with an integrated [[graphics processing unit|graphics processor]] from [[ATI Technologies|ATI]].

== Main features ==

* 64-bit, dual-threaded core

* 3.2 GHz GHZtypical clockrate

* 32 KB [[CPU cache|L1 instruction cache]]

* 32 KB [[CPU cache|L1 data cache]]

* 512 KB unified L2 cache, [[Set-associative#Associativity|8-way set associative]] in the PPE variant.

* Compatible with 64-bit PowerPC ISA v.2.02 ([[POWER4]] and [[PowerPC 970]])<ref name="the-ppe">{{cite book |url= https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 |title=Practical Computing on the Cell Broadband Engine |first=Sandeep |last=Koranne |chapter=The Power Processing Element (PPE) |chapter-url=https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 |isbn=978-1-4419-0307-5 |publisher=[[Springer Science+Business Media]] |date=July 15, 2009|pages=17–34 |doi=10.1007/978-1-4419-0308-2_2 }}</ref>{{rp|page=17}}

* [[AltiVec]] [[SIMD]] functionality

== Execution units ==

* 64-bit, dual-threaded

* [[Branch predictor|Branch Unit (BRU)]]

* 3.2 GHZ clockrate

* [[Arithmetic logic unit|Fixed Point Integer Unit (FXU)]]

* 32 KB L1 Instruction Cache

* [[Load–store unit|Load and Store Unit (LSU)]]

* 32 KB L1 Data Cache

* [[Floating-point unit|Floating-Point Unit (FPU)]]

* 512 KB Unified L2 Cache, 8-way set associative

* [[AltiVec|Vector Media Extension Unit (VMX)]]

* Compatible with PowerPC 970 MP/FX applications

* Includes Altivec multimedia extensions

== Functional unitsIn-order ==

{{Main | Out-of-order execution}}

The Power Processing ElementPPU is an Inin-Orderorder processor, but it has some unique traits which allow it to achieve some benefits of Outout-of-Orderorder execution without expensive re-ordering hardware. Upon reaching an L1 cache miss -– it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe -– a side path that allows it to execute instructions that would normally cause [[bubble (computing)|pipeline stalls]] without holding up the rest of the [[instruction pipeline|pipeline]]. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on.

== The PPE's pipeline ==

* Branch Unit (BRU)

The PPE has a 23-stage general pipeline with an additional 11 stages possible for microcode and an additional 4 stages possible for branch prediction.<ref>{{cite web |url=http://www.ibm.com/developerworks/library/pa-cellperf/ |title=Cell Broadband Engine Architecture and its first implementation |first1=Thomas |last1=Chen |first2=Ram |last2=Raghavan |first3=Jason |last3=Dale |first4=Eiji |last4=Iwata |website=IBM DeveloperWorks |archive-url=https://web.archive.org/web/20151208051244/http://www.ibm.com/developerworks/library/pa-cellperf/ |archive-date=2015-12-08 |url-status=dead}}</ref>

* Fixed Point Integer Unit (FXU)

* Load and Store Unit (LSU)

* Floating-Point Unit (FPU)

* Vector Media Extension Unit (VMX)

== In-OrderMultithreading ==

ItThe canPPU runruns two [[simultaneous multithreading|hardware threads]] simultaneously. The [[Processor register|main registers]] for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated though -– so it is still just a single-core design.<ref>http://www.springer.com/cda/content/document/cda_downloaddocument/9781441903075-c1.pdf?SGWID name=0"the-0-45-771056-p173894926<ppe" /ref>

== Floating-point Point Capacitycapacity ==

The Power Processing Element is an In-Order processor, but it has some unique traits which allow it to achieve some benefits of Out-of-Order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It also has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause pipeline stalls without holding up the rest of the pipeline.

Its [[64-bit]] [[double-precision floating-point format|double-precision]] floating-point unit, and [[128-bit]] VMX unit (using the [[AltiVec]] instruction set), can perform a theoretical 12 floating-point operations per cycle, as all IBM PowerPCits floating-point unitsunit can do floating-point mulitplymultiply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles *× 12 = 38.4 billion floating-point operations/second.

The PPU is enhanced in the [[Cell processor#PowerXCell 8i|PowerXCell 8i]] processor to be able to make single cycle double precision floating point operations, tailored for high performance computing in supercomputers.

== Like a Dual-Core Processor ==

The VMX unit in the [[Xenon (processor)|XCPU]] in the Xbox 360 is enhanced with 128 [[Processor register|registers]] and is not entirely compatible with regular AltiVec.

It can run two threads simultaneously. The main registers for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated though - so it is still just a single-core design.<ref>http://www.springer.com/cda/content/document/cda_downloaddocument/9781441903075-c1.pdf?SGWID=0-0-45-771056-p173894926</ref>

== Floating Point Capacity ==

Its 64-bit floating-point unit, and 128-bit VMX unit, can perform a theoretical 12 floating-point operations per cycle, as all IBM PowerPC floating-point units can do floating-point mulitply-adds, and come no smaller than 64-bits. That gives 3.2 billion clock cycles * 12 = 38.4 billion floating-point operations/second.

==References==

{{Reflist}}

{{Cell microprocessor segments}}

[[Category:Cell BE architecture]]

[[Category:IBM microprocessors]]

[[Category:PowerPC architecture]]

[[Category:Xbox 360 hardware]]