Glossary of reconfigurable computing: Difference between revisions

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{{Short description|none}}

{{See also|Glossary of computers}}

{{unreferenced|date=May 2017}}

'''ReconfigurableThis computingis a terminology''' lists someglossary of the terms and expressions that are used in the field of [[Reconfigurable computing]]''' and reconfigurable computing systems, as opposed to the traditional [[vonVon Neumann architecture]] computing architectures.

{{glossary}}

'''Reconfigurable computing terminology''' lists some of the terms and expressions that are used in the field of [[Reconfigurable computing]] and reconfigurable computing systems, as opposed to traditional [[von Neumann]] computing architectures.

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{{term|1=Term}}

{{ghat|1="hat" commment, for "also known as" entries and the like}}

{{defn|1=Definition.}}

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{{gloss}}

{{term|1=Aggregate On-chip memory}}

{{defn|1=Refers to total on-chip memory available for multi-FPGA systems.}}

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{{defn|1=Code segments/pieces that are meant to run on the microprocessor. This could include simulation/emulation runs, which are executing on the processor. Alternatively, this word could be used to encompass the processes of synthesis, and place and route for reconfigurable devices.}}

{{term|1=[[Configware/Software-Co-Compilation|Co-compilation]]}}

{{defn|1=[[Configware/Software-Co-Compilation]]: Compilation for generating [[Software]] Code and [[Configware]] Code, including automatic Software/Configware partitioning.}}

{{term|1=[[Configware]]}}

{{defn|1=Source programs for Configuration. Being of structural nature, Configware is the counterpart of Software (being of procedural nature).}}

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{{term|1=[[Emulator|Emulation]]/[[Simulation]]}}

{{ghat|1=also known as Simulation, Modeling.}}

{{defn|1=Process of mimicking the behavior of an [[Application-specific integrated circuit|ASIC]] design on [[FPGA]]-based hardware or a processor-based system or (in the case of simulation) a computer.}}

{{term|1=[[Flowware]]}}

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{{defn|1=Another term for Reconfigurable Devices, indicating [[Reconfigurability]] in contrast to "[[computer hardware|hardware]]".}}

{{term|1=[[CPU cache|On-chip memory]]}}

{{ghat|1=also known as Block RAM, Cache}}

{{defn|1=This term should refer to memory that is available on-chip within a single chip (whether it be BRAM Slices or SRAM slices). The term cache should be reserved purely for memory directly attached to processors on the system/host side.}}

{{term|1=[[Place and Route]]}}

{{defn|1=Process of converting a [[netlist]] into physically mapped and placed components on the [[FPGA]] or [[Reconfigurable Data Path Array|rDPA]], ending in the creation of a [[bitstream]].}}

{{term|1=Reconfigurable Computer}}

{{defn|1=An Estrin architecture reconfigurable computer typically pairs a conventional microprocessor host computer with a reconfigurable co-processor, such as an [[FPGA]] or [[Reconfigurable Data Path Array|rDPA]] board. The co-processor can be reconfigured to perform different computations during execution of a host computer program by loading appropriate bitstreams. Newer FPGA-based architectures eliminate the need for a host processor by providing mechanisms to configure the device on boot from flash, and to directly support essential interfaces to memory and network resources via a bus configured in the device fabric.

AfairlyFairly recent market has developed for low-power reconfigurable system-on-chip ([[System-on-a-chip|SoC]]) devices that manufacturers can customize to their product applications, which are typically portable consumer media electronics. The devices typically incorporate one or more von Neumann processors, and provide mechanisms to extend the processor(s) instruction set and/or interface the device to other subsystems in the product. While these devices are technically "reconfigurable processors," they are really designed to be configured once during production, or to be reconfigured as part of a field upgrade, but not to be reconfigured on-the-fly.}}

{{term|1=Reconfigurable Computing}}

{{defn|1=A computing paradigm employing reconfigurable devices such as FPGAs or rDPAs to process data. A different bitstream can be loaded during the execution of a program or to run a different program on the fly. Estrin architecture reconfigurable computers include conventional von Neumann processors as main or control processors, and typically use one or more reconfigurable devices as co-processors. Newer FPGA-based architectures eliminate the need for a host processor by providing mechanisms to configure the device on boot from flash, and to directly support essential interfaces to memory and network resources via a bus configured in the device fabric. Providing a stable and stateful computational platform within a reconfigurable device requires, however, ''partial reconfigurability'' - that is, the ability to reconfigure only that portion of the device that implements an application, while leaving unchanged the portion of the device that implements the platform - the memory and network interfaces, the device drivers, and so forth. Current FPGA devices allow partial reconfiguration, but implementing designs that can effectively use this feature is still a tough exercise in system-on-chip design.}}

{{term|1=Reconfigurable Device}}

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{{term|1=Reconfiguration}}

{{defn|1=Configuration, programming, re-programming (also see [[Configware]]).}}

{{term|1=System Memory/Host Memory}}

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{{defn|1=Process of creating a netlist from a circuit description described using [[Hardware description language|HDL]]s (Hardware Description Language), [[High-level programming language|HLL]]s (High Level Language), [[Graphical user interface|GUI]] (Graphical User Interfaces).}}

{{glossendglossary end}}

==See also==

* [[Glossary of computer terms]]

{{See also|GlossaryGlossaries of computers}}

[[Category:Reconfigurable computing]]

[[Category:Glossaries of computers|Reconfigurable computing]]

[[Category:Wikipedia glossaries using description lists]]