Template:Infobox CPU architecture/doc: Difference between revisions

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{{Documentation subpage}}

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This template is for CPU architectures.

{{Lua|Module:Infobox|Module:InfoboxImage|Module:Check for unknown parameters}}

This template is for CPU architectures[[instruction set architecture]]s.

=== Usage ===

<syntaxhighlight lang="wikitext">

<pre>

{{Infobox CPU architecture

| name =

| designerimage =

| bits image_size =

| introducedalt =

| versioncaption =

| design designer =

| typebits =

| encoding introduced =

| branchingversion =

| endiannessdesign =

| type =

| pageencoding size =

| extensionsbranching =

| open endianness =

| registerspage size =

| gpr extensions =

| fpropen =

| predecessor =

| successor =

| registers =

| gpr =

| fpr =

| vpr =

}}

</syntaxhighlight>

</pre>

=== Description ===

<syntaxhighlight lang="wikitext">

<pre>

{{Infobox CPU architecture

| name = Name of architecture, e.g. x86, SPARC, PowerPC, MIPS, ARM

| designer = Designer of the architecture

| bits = Width of accumulator/general registers/stack top, e.g. 32-bit, 64-bit

| introduced = Year introduced

| version = Version/revision of architecture/ISA

| design = Design strategy, e.g. RISC, CISC

| type = Type of architecture, e.g. Register-Register, Register-Memory, Memory-Memory

| encoding = Instruction set encoding, e.g. Fixed or Variable

| branching = Branching evaluation, e.g. Condition register, Condition code, Compare and branch

| endianness = Byte ordering, i.e. Little, Big, Bi

| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc

| page size = Primary size of page, i.e. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

| predecessor = Earlier architecture(s) this one is based on, if it has a separate page

| extensions = ISA extensions, i.e. MMX, SSE, AltiVec, etc

| successor = Later architecture(s) based primarily on this one, if it has a separate page

| open = Is the architecture open or not? (as in free or proprietary)

| registers = Number and size of processor registers

| registers = Number and size of processor registers
| gpr = Number of general-purpose registers (and size, if not indicated by bits=)

| fpr = Number of floating-point registers (and size, if not indicated by bits=)

| vpr = Number of vector registers (and size, if not indicated by bits=)

}}

</syntaxhighlight>

</pre>

All fields are optional.

Line 63 ⟶ 74:

| endianness = Bi (Big → Bi)

| page size = 8 KiB

| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0

| open = Yes

| gpr = 31 (G0 = 0; non-global registers use [[register window]]s)

| fpr = 32

}}

<syntaxhighlight lang="wikitext">

<pre>

{{Infobox CPU architecture

| name = SPARC

Line 82 ⟶ 92:

| endianness = Bi (Big → Bi)

| page size = 8 KiB

| extensions = [[Visual Instruction Set|VIS]] 1.0, 2.0, 3.0

| open = Yes

Line 88 ⟶ 97:

| fpr = 32

}}

</syntaxhighlight>

</pre>

=== Parameters ===

Line 101 ⟶ 110:

; encoding: Instruction set encoding, e.g. Fixed or Variable

; branching: Branching evaluation, e.g. Condition register, Condition code, Compare and branch

; endianness: Byte ordering, i.e.g. Little, Big, Bi

; page size: Primary size of page, i.e.g. 4 KiB, 2 MiB, 1 GiB; does not include "huge pages" and other extensions

; extensions: ISA extensions, i.e.g. MMX, SSE, AltiVec, etc

; open: Is the architecture open or not? (as in free or proprietary)

; predecessor: Earlier architecture(s) this one is based on, if it has a separate page

; successor: Later architecture(s) based primarily on this one, if it has a separate page

; registers: Number and size of processor registers

; gpr: Number of general-purpose registers (and size, if not indicated by bits=)

; fpr: Number of floating-point registers (and size, if not indicated by bits=)

; vpr: Number of vector registers (and size, if not indicated by bits=)

=== See also ===

* {{Ltstl|Infobox CPU}} — for [[central processing unit]]s

* {{Ltstl|Infobox ComputerCPU Hardware Busseries}} for [[Bus (computing)|computer bus]]es

* {{tl|Infobox computer hardware bus}} — for [[Bus (computing)|computer bus]]es

<includeonly>{{Sandbox other||

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[[Category:ComputingComputer hardware infobox templates|CPU architecture]]

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