Interrupt vector table: Difference between revisions

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{{about|the general concept|its implementation found in x86 processors|Interrupt descriptor table}}

[[File:X86 Interrupt Vector Table.svg|thumb]]

An '''interrupt vector table''' ('''IVT''') is a [[data structure]] that associates a list of [[interrupt handler]]s with a list of [[interrupt request]]s in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler (also known as [[Interrupt_handler|ISR]]). While the concept is common across processor architectures, IVTs may be implemented in architecture-specific fashions. For example, a [[dispatch table]] is one method of implementing an interrupt vector table.

Interrupts are assigned a number between 0 to 255. The interrupt vectors for each interrupt number are stored in the lower 1024 bytes of main memory. For example, interrupt 0 is stored from 0000:0000 to 0000:0003, interrupt 1 from 0000:0004 to 0000:0007, and so on.

{|class="wikitable"

|+ Interrupt List

|-

!Interrupt Number

!IVT Address

!Interrupt Name

|-

|0

|00-03

|CPU divide by zero

|-

|1

|04-07

|Debug single step

|-

|2

|08-0B

|Non Maskable Interrupt (NMI input on processor)

|-

|3

|0C-0F

|Debug breakpoints

|-

|4

|10-13

|Arithmetic overflow

|-

|5

|14-17

|BIOS provided Print Screen routine

|-

|6

|18-1B

|Reserved

|-

|7

|1C-1F

|Reserved

|-

|8

|20-23

|IRQ0, Time of day hardware services

|-

|9

|24-27

|IRQ1, Keyboard Interface

|-

|A

|28-2B

|IRQ2, ISA Bus cascade services for second 8259

|-

|B

|2C-2F

|IRQ3, Com 2 hardware

|-

|C

|30-33

|IRQ4, Com1 hardware

|-

|D

|34-37

|IRQ5, LPT2, Parallel port hardware (Hard Disk on XT)

|-

|E

|38-3B

|IRQ6, Floppy Disk adaptor

|-

|F

|3C-3F

|IRQ7, LPT1, Parallel port hardware

|-

|10

|40-43

|Video services, see note 1

|-

|11

|44-47

|Equipment check

|-

|12

|48-4B

|Memory size determination

|-

|13

|4C-4F

|Floppy I/O routines

|-

|14

|50-53

|Serial port I/O routines

|-

|15

|54-57

|PC used for Cassette tape services

|-

|16

|58-5B

|Keyboard I/O routines

|-

|17

|5C-5F

|Printer I/O routines

|-

|18

|60-63

|Points to basic interpreter in a "real" IBM PC

|-

|19

|64-67

|Bootstrap loader

|-

|1A

|68-6B

|Time of day services

|-

|1B

|6C-6F

|Services Ctrl-Break service

|-

|1C

|70-73

|Timer tick (provides 18.2 ticks per second)

|-

|1D

|74-77

|Video parameters

|-

|1E

|78-7B

|Disk parameters

|-

|1F

|7C-7F

|Video graphics

|-

|20

|80-83

|Program termination (obsolete)

|-

|21

|84-87

|All DOS services available through this Interrupt

|-

|22

|88-8B

|Terminate address

|-

|23

|8C-8F

|Ctrl-Break exit address

|-

|24

|90-93

|Critical error handler

|-

|25

|94-97

|Read logical sectors

|-

|26

|98-9B

|Write logical sectors

|-

|27

|9C-9F

|Terminate and stay resident routines (obsolete)

|-

|28 to 3F

|A0-A3 to FC-FF

|Reserved for DOS

|-

|40 to 4F

|100-103 to 13C-13F

|Reserved for BIOS

|-

|50

|140-143

|Reserved for BIOS

|-

|51

|144-147

|Mouse functions

|-

|52 to 59

|148-14B to 164-167

|Reserved for BIOS

|-

|5A

|168-16B

|Reserved for BIOS

|-

|}

==Background==

Most processors have an interrupt vector table, including chips from [[Intel]], [[AMD]], [[Infineon Technologies|Infineon]], Microchip<ref>[http://ww1.microchip.com/downloads/en/DeviceDoc/70189c.pdf "dsPIC33F Family Reference Manual"] section 29.1.1 Interrupt Vector Table

</ref> [[AVR microcontrollers|Atmel]],<ref>[http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html "AVR Libc User Manual"] section: Introduction to avr-libc's interrupt handling</ref> NXP, [[ARM architecture|ARM]],<ref>{{Cite web|title=Documentation – Arm Developer|url=https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/vector-table|access-date=2020-07-26|website=developer.arm.com}}</ref><ref>{{Cite web|title=Documentation – Arm Developer – AArch64 exception vector table|url=https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table?lang=en|access-date=2020-07-26|website=developer.arm.com}}</ref> etc.

==Interrupt handlers==

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== External links ==

*[http://developer.intel.com/design/pentium/manuals/ Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide] {{Webarchive|url=https://web.archive.org/web/20090216132436/http://developer.intel.com/design/pentium/manuals/ |date=2009-02-16 }}

** [https://web.archive.org/web/20081221050950/http://download.intel.com/design/processor/manuals/253668.pdf Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:System Programming Guide, Part 1] (see CHAPTER 6, INTERRUPT AND EXCEPTION HANDLING and CHAPTER 10, ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER)]

*{{webarchive|url=https://web.archive.org/web/20160304054440/http://www.tcd.ie/Engineering/Courses/BAI/JS_Subjects/3D1/Documents/Handouts/ExVecTab.pdf|title=Motorola M68000 Exception and Vector Table}}