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Most processors have an interrupt vector table, including chips from [[Intel]], [[AMD]], [[Infineon Technologies|Infineon]], Microchip<ref>[http://ww1.microchip.com/downloads/en/DeviceDoc/70189c.pdf "dsPIC33F Family Reference Manual"] section 29.1.1 Interrupt Vector Table
</ref> [[AVR microcontrollers|Atmel]],<ref>[http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html "AVR Libc User Manual"] section: Introduction to avr-libc's interrupt handling</ref> NXP, [[ARM architecture|ARM]],<ref>{{Cite web|title=Documentation – Arm Developer|url=https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/vector-table|access-date=2020-07-26|website=developer.arm.com}}</ref><ref>{{Cite web|title=Documentation – Arm Developer – AArch64 exception vector table|url=https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table?lang=en|access-date=2020-07-26|website=developer.arm.com}}</ref> etc.
==Interrupt handlers==
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== External links ==
*[http://developer.intel.com/design/pentium/manuals/ Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide] {{Webarchive|url=https://web.archive.org/web/20090216132436/http://developer.intel.com/design/pentium/manuals/ |date=2009-02-16 }}
** [https://web.archive.org/web/20081221050950/http://download.intel.com/design/processor/manuals/253668.pdf Intel 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:System Programming Guide, Part 1] (see CHAPTER 6, INTERRUPT AND EXCEPTION HANDLING and CHAPTER 10, ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER)]
*{{webarchive|url=https://web.archive.org/web/20160304054440/http://www.tcd.ie/Engineering/Courses/BAI/JS_Subjects/3D1/Documents/Handouts/ExVecTab.pdf|title=Motorola M68000 Exception and Vector Table}}
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