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Line 7: Most processors have an interrupt vector table, including chips from [[Intel]], [[AMD]], [[Infineon Technologies\|Infineon]], Microchip<ref>[http://ww1.microchip.com/downloads/en/DeviceDoc/70189c.pdf "dsPIC33F Family Reference Manual"] section 29.1.1 Interrupt Vector Table </ref> [[AVR microcontrollers\|Atmel]],<ref>[http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html "AVR Libc User Manual"] section: Introduction to avr-libc's interrupt handling</ref> NXP, [[ARM architecture\|ARM]],<ref>{{Cite web\|title=Documentation – Arm Developer\|url=https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/vector-table\|access-date=2020-07-26\|website=developer.arm.com}}</ref><ref>{{Cite web\|title=Documentation – Arm Developer – AArch64 exception vector table\|url=https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table?lang=en\|access-date=2020-07-26\|website=developer.arm.com}}</ref> etc. ==Interrupt handlers==

Interrupt vector table: Difference between revisions