Interrupt vector table: Difference between revisions

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{{short description|Data structure}}

{{about|the general concept|its implementation found in x86 processors|Interrupt descriptor table}}

[[File:X86 Interrupt Vector Table.svg|thumb]]

An '''interrupt vector table''' ('''IVT''') is a [[data structure]] that associates a list of [[interrupt handler]]s with a list of [[interrupt request]]s in a table of interrupt vectors. AnEach entry of the interrupt vector table, called an interrupt vector, is the address of thean interrupt handler (also known as [[Interrupt_handler|ISR]]). While the concept is common across processor architectures, each IVTIVTs may be implemented in an architecture-specific fashionfashions. For example, a [[dispatch table]] is one method of implementing an interrupt vector table.

==Background==

Most processors have an interrupt vector table, including chips from [[Intel]], [[AMD]], [[Infineon Technologies|Infineon]], Microchip<ref>[http://ww1.microchip.com/downloads/en/DeviceDoc/70189c.pdf "dsPIC33F Family Reference Manual"] section 29.1.1 Interrupt Vector Table

</ref> [[AVR microcontrollers|Atmel]],<ref>[http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html "AVR Libc User Manual"] section: Introduction to avr-libc's interrupt handling</ref> FreescaleNXP, AMD,[[ARM Intelarchitecture|ARM]],<ref>{{Cite web|title=Documentation – Arm Developer|url=https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/vector-table|access-date=2020-07-26|website=developer.arm.com}}</ref><ref>{{Cite web|title=Documentation – Arm Developer – AArch64 exception vector table|url=https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table?lang=en|access-date=2020-07-26|website=developer.arm.com}}</ref> etc.

==Interrupt handlers==

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===="Predefined"====

The "predefined" method loads the [[program counter]] (PC) directly with the address of some entry inside the interrupt vector table. The [[jump table]] itself contains executable code. While in principle an extremely short interrupt handler could be stored entirely inside the interrupt vector table, in practice the code at each and every entry is "JMPa address"single wherejump theinstruction addressthat isjumps to the address of thefull interrupt service routine (ISR) for that interrupt. The Intel [[Intel 8080|8080]],<ref>{{Cite book|title=Intel 8080 Microcomputer Systems User's Manual|date=September 1975|publisher=Intel Corporation|ol = 24210843M|pages=2–11 Interrupt Sequences|oclc=2058546}}</ref> Atmel AVR<ref>Roger L. Traylor. [http://web.engr.oregonstate.edu/~traylor/ece473/lectures/interrupts.pdf "Interrupts: AVR interrupt servicing"]</ref><ref> Gary Hill. [httphttps://wwwhome.csulb.edu/~hill/ee346/Lectures/10_ATmega328P10%20ATmega32U4%20Interrupts.pdf "Atmel AVR Interrupt and Timing Subsystems: ATMEGA328P interrupt vector table"]</ref> and all 8051 and Microchip microcontrollers<ref name="huang">{{cite book |last=Huang |first=Han-Wat |title=Pic Microcontroller: An Introduction to Software and Hardware Interfacing |url=httphttps://books.google.com/books?id=CB9GaAU1dwsC&pg=PA247 |accessdateaccess-date=22 April 2013 |year=2005 |publisher=Cengage Learning |isbn=978-1-4018-3967-3 |page=247}}</ref> use the predefined approach.

===="Fetch"====

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===="Interrupt acknowledge"====

TheFor the "interrupt acknowledge" method, the external device gives the CPU an interrupt handler number. The interrupt acknowledge method is used by the Intel Pentium and many older microprocessors.<ref name="huang" />

When the CPU is affected by an [[interrupt]], it looks up the [[interrupt handler]] in the interrupt vector table, and transfers control to it.

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== See also ==

* [[Interrupt Descriptordescriptor Tabletable]] (x86 Architecture implementation)

== References ==

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== External links ==

*[http://developer.intel.com/design/pentium/manuals/ Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide] {{Webarchive|url=https://web.archive.org/web/20090216132436/http://developer.intel.com/design/pentium/manuals/ |date=2009-02-16 }}

** [https://web.archive.org/web/20081221050950/http://download.intel.com/design/processor/manuals/253668.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:System Programming Guide, Part 1] (see CHAPTER 6, INTERRUPT AND EXCEPTION HANDLING and CHAPTER 10, ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER)]

*[{{webarchive|url=https://web.archive.org/web/20160304054440/http://www.tcd.ie/Engineering/Courses/BAI/JS_Subjects/3D1/Documents/Handouts/ExVecTab.pdf |title=Motorola M68000 Exception and Vector Table]}}

[[Category:Interrupts]]