Interrupt vector table: Difference between revisions

Revision as of 13:47, 29 January 2019

Latest revision as of 01:28, 4 November 2024

(25 intermediate revisions by 20 users not shown)

Line 1:

{{short description|Data structure}}

{{about|the general concept|its implementation found in x86 processors|Interrupt descriptor table}}

[[File:X86 Interrupt Vector Table.svg|thumb]]

An "'''interrupt vector table"''' ('''IVT''') is a [[data structure]] that associates a list of [[interrupt handler]]s with a list of [[interrupt request]]s in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler (also known as [[Interrupt_handler|ISR]]). While the concept is common across processor architectures, IVTs may be implemented in architecture-specific fashions. For example, a [[dispatch table]] is one method of implementing an interrupt vector table.

==Background==

Most processors have an interrupt vector table, including chips from [[Intel]], [[AMD]], [[Infineon Technologies|Infineon]], Microchip<ref>[http://ww1.microchip.com/downloads/en/DeviceDoc/70189c.pdf "dsPIC33F Family Reference Manual"] section 29.1.1 Interrupt Vector Table

</ref> [[AVR microcontrollers|Atmel]],<ref>[http://www.nongnu.org/avr-libc/user-manual/group__avr__interrupts.html "AVR Libc User Manual"] section: Introduction to avr-libc's interrupt handling</ref> NXP, [[ARM architecture|ARM]],<ref>{{Cite web|title=Documentation – Arm Developer|url=https://developer.arm.com/documentation/dui0552/a/the-cortex-m3-processor/exception-model/vector-table|access-date=2020-07-26|website=developer.arm.com}}</ref><ref>{{Cite web|title=Documentation – Arm Developer – AArch64 exception vector table|url=https://developer.arm.com/documentation/100933/0100/AArch64-exception-vector-table?lang=en|access-date=2020-07-26|website=developer.arm.com}}</ref> etc.

==Interrupt handlers==

Line 18 ⟶ 19:

===="Predefined"====

The "predefined" method loads the [[program counter]] (PC) directly with the address of some entry inside the interrupt vector table. The [[jump table]] itself contains executable code. While in principle an extremely short interrupt handler could be stored entirely inside the interrupt vector table, in practice the code at each entry is a single jump instruction that jumps to the full interrupt service routine (ISR) for that interrupt. The Intel [[Intel 8080|8080]],<ref>{{Cite book|url=https://openlibrary.org/books/OL24210843M/Intel_8080_microcomputer_systems_user%27s_manual|title=Intel 8080 Microcomputer Systems User's Manual|last=|first=|date=September 1975|publisher=Intel Corporation|year=|isbn=|___locationol = 24210843M|pages=2-112–11 Interrupt Sequences|oclc=2058546}}</ref>, Atmel AVR<ref>Roger L. Traylor. [http://web.engr.oregonstate.edu/~traylor/ece473/lectures/interrupts.pdf "Interrupts: AVR interrupt servicing"]</ref><ref> Gary Hill. [httphttps://webhome.csulb.edu/~hill/ee346/Lectures/10%20ATmega328P20ATmega32U4%20Interrupts.pdf "Atmel AVR Interrupt and Timing Subsystems: ATMEGA328P interrupt vector table"]</ref> and all 8051 and Microchip microcontrollers<ref name="huang">{{cite book |last=Huang |first=Han-Wat |title=Pic Microcontroller: An Introduction to Software and Hardware Interfacing |url=https://books.google.com/books?id=CB9GaAU1dwsC&pg=PA247 |accessdateaccess-date=22 April 2013 |year=2005 |publisher=Cengage Learning |isbn=978-1-4018-3967-3 |page=247}}</ref> use the predefined approach.

===="Fetch"====

Line 32 ⟶ 33:

== See also ==

* [[Interrupt Descriptordescriptor Tabletable]] (x86 Architecture implementation)

== References ==

Line 38 ⟶ 39:

== External links ==

*[http://developer.intel.com/design/pentium/manuals/ Intel® Architecture Software Developer's Manual, Volume 3: System Programming Guide] {{Webarchive|url=https://web.archive.org/web/20090216132436/http://developer.intel.com/design/pentium/manuals/ |date=2009-02-16 }}

** [https://web.archive.org/web/20081221050950/http://download.intel.com/design/processor/manuals/253668.pdf Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A:System Programming Guide, Part 1] (see CHAPTER 6, INTERRUPT AND EXCEPTION HANDLING and CHAPTER 10, ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER)]

*[{{webarchive|url=https://web.archive.org/web/20160304054440/http://www.tcd.ie/Engineering/Courses/BAI/JS_Subjects/3D1/Documents/Handouts/ExVecTab.pdf |title=Motorola M68000 Exception and Vector Table]}}

[[Category:Interrupts]]