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* Only functions annotated with sieve or immediate can be called.
Delaying side-effects removes many small dependencies which would usually impede automatic parallelization. Reads and writes can be safely reordered by the compiler as to allow better use of various data movement mechanisms, such as [[Direct Memory Access]](DMA). In addition, [[alias analysis]] and [[dataflow analysis]] can be simplified [http://www.cl.cam.ac.uk/~al407/research/papers/eupar07.pdf]{{Dead link|date=November 2024 |bot=InternetArchiveBot |fix-attempted=yes }}. The compiler can then split up code within the sieve block much easier, to exploit parallelism.
==Memory Configuration==
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==Parallelization and Scalability==
The sieve compiler can split code within a sieve block into chunks either implicitly or explicitly though a 'splithere' statement. For instance, the following example shows parallelizing a loop:
<
sieve
{
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}
}
</syntaxhighlight>
The compiler will implicitly add a splitpoint above the for loop construct body, as an entry point. Similarly one will be added after as an exit point.
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==Determinism==
Determinism is an unusual feature of the Sieve System. If executing a parallel Sieve program on a multi core machine yields a bug, the bug will not disappear when run on a single core to aid [[debugging]][https://web.archive.org/web/20070321082311/http://www.codeplay.com/downloads_public/sievepaper-2columns-normal.pdf][http://www.cl.cam.ac.uk/~al407/research/papers/eupar07.pdf]{{Dead link|date=November 2024 |bot=InternetArchiveBot |fix-attempted=yes }}. This has the advantage of eliminating [[race conditions]], one of the most common bugs in [[concurrent programming]]. The removal of the need to consider [[concurrency control]] structures within a sieve block can speed up development time and results in safer code.
==Supported Systems==
The system is designed for hierarchical based systems with homogeneous or heterogeneous CPU cores which have local memories, connected via DMA engines or similar memory transfer models.
Sieve has been shown [https://web.archive.org/web/20070827225352/http://www.codeplay.com/technology/sievebenchmarks.html] successfully operating on multi-core x86 systems, the [[Ageia]] [[PhysX]] [[Physics Processing Unit]], and the IBM [[Cell microprocessor]]. [[ANSI C]] is generated if a compiler [[code generation (compiler)|code generator]] is not available for a certain target platform. This allows for autoparallelization using existing C compilation toolkits [http://mgrid.feis.herts.ac.uk/wp-content/scott.ppt]{{dead link|date=May 2018 |bot=InternetArchiveBot |fix-attempted=yes }}.
==See also==
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==References==
*[http://www.cl.cam.ac.uk/~al407/research/papers/hppc07.pdf Auto-parallelisation of Sieve C++ Programs]{{Dead link|date=November 2024 |bot=InternetArchiveBot |fix-attempted=yes }} Alastair Donaldson, Anton Lokhmotov, Colin Riley, Andrew Cook. In Proceedings of the Euro-Par Workshop Highly Parallel Processing on a Chip (HPPC'07), Rennes, France, August 2007. Lecture Notes in Computer Science 4854, 2007.
*[http://www.cl.cam.ac.uk/~al407/research/papers/eupar07.pdf Delayed Side-effects Ease Multi-core Programming]{{Dead link|date=November 2024 |bot=InternetArchiveBot |fix-attempted=yes }} Anton Lokhmotov, Alan Mycroft, Andrew Richards. In Proceedings of the 13th International Euro-Par Conference, Rennes, France, August 2007. Lecture Notes in Computer Science 4641, 641-650, 2007.
*[https://www.cs.cmu.edu/~damp/finalPapers/lindley.pdf Implementing deterministic declarative concurrency using sieves] S. Lindley. In proceedings of DAMP 2007: Workshop on Declarative Aspects of Multicore Programming Nice, France, January 2007.
*[https://web.archive.org/web/20070321082311/http://www.codeplay.com/downloads_public/sievepaper-2columns-normal.pdf The Codeplay Sieve C++ Parallel Programming System] A. Richards. White paper, 2006.
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