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{{Use American English|date = March 2019}}▼
{{Short description|Prototyping integrated circuit designs on FPGA}}
{{Further|Field-programmable gate array}}
▲{{Use American English|date = March 2019}}
{{Use mdy dates|date = March 2019}}
{{original research|date=September 2012}}
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{{Essay-like|date=December 2021}}
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'''Field-programmable gate array prototyping''' ('''FPGA prototyping'''), also referred to as FPGA-based prototyping, ASIC prototyping or [[System on a chip|system-on-chip]] (SoC) prototyping, is the method to [[prototype]] system-on-chip and [[application-specific integrated circuit]] designs on [[Field-programmable gate array|FPGAs]] for hardware [[verification and validation|verification]] and early [[software development]].
Verification methods for [[computer hardware|hardware]] design as well as early [[software]] and [[firmware]] co-design have become mainstream. Prototyping SoC and ASIC designs with one or more FPGAs and [[electronic design automation]] (EDA) software has become a good method to do this.<ref>{{Cite web|url=https://numato.com/blog/differences-between-fpga-and-asics/|title=FPGA vs ASIC: Differences between them and which one to use? – Numato Lab Help Center|website=numato.com|date=July 17, 2018 |language=en-US|access-date=2018-10-17}}</ref>
==Importance==
#Running a SoC design on FPGA prototype is a reliable way to ensure that it is functionally correct. This is compared to designers only relying on [[Electronic circuit simulation|software simulations]] to verify that their hardware design is sound. About a third of all current SoC designs are fault-free during first silicon pass, with nearly half of all re-spins caused by functional logic errors.<ref name ="soc">{{Cite web |url=http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |title=
#[[Time to market|Time-to-market]] (TTM) is reduced from FPGA prototyping: In today's technological driven society, new products are introduced rapidly, and failing to have a product ready at a given
#Development cost: Development cost of 90-nm ASIC/SoC design tape-out is around $20 million, with a mask set costing over $1 million alone.<ref name= soc/> Development costs of 45-nm designs are expected to top $40 million. With increasing cost of mask sets, and the continuous decrease of IC size, minimizing the number of re-spins is vital to the development process.
==Design for prototyping==
'''Design for prototyping'''<ref>{{cite web|url=http://www.newelectronics.co.uk/electronics-technology/prototyping-system-designs-on-fpgas/32395/|title=Prototyping System Designs on FPGAs|date=2011-03-22|publisher=New Electronics|accessdate=2011-03-22|archive-date=March 6, 2012|archive-url=https://web.archive.org/web/20120306210417/http://www.newelectronics.co.uk/electronics-technology/prototyping-system-designs-on-fpgas/32395/|url-status=dead}}</ref> ('''DFP''') refers to designing systems that are amenable to [[prototyping]]. Many of the obstacles facing development teams who adopt FPGA prototypes can be distilled down to three "laws":
* SoCs are larger than FPGAs
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Due to increased circuit complexity, and time-to-market shrinking, the need for verification of application-specific-integrated-circuit (ASIC) and system-on-chip (SoC) designs is growing. Hardware platforms are becoming more prominent amongst verification engineers due to the ability to test system designs at-speed with on-chip bus clocks, as compared to simulation clocks which may not provide an accurate reading of system behavior.<ref>{{Cite news|url=http://www.eejournal.com/archives/articles/20110825-mathworks/|title=Best Practices for FPGA Prototyping of MATLAB and Simulink Algorithms|date=2011-08-25|work=EEJournal|access-date=2018-10-08|language=en-US}}</ref> These multi-million gate designs usually are placed in a multi-FPGA prototyping platform with six or more FPGAs, since they are unable to fit entirely onto a single FPGA. The fewer number of FPGAs the design has to be partitioned to reduce the effort from the design engineer.<ref name= Aldec/> To the right is a picture of a FPGA-based prototyping platform utilizing a dual-FPGA configuration. [[File:Aldec HES7 ASIC Prototyping Platform.jpg|thumb|alt=Aldec FPGA-based prototyping platform with dual FPGA configuration.|Aldec's HES-7 ASIC prototyping solution]]
System RTL designs or netlists will have to be partitioned onto each FPGA to be able to fit the design onto the prototyping platform.<ref>{{Cite web |url=http://www.electronicsweekly.com/Articles/20/12/2007/42539/fpga-prototyping-its-about-the-software.htm |title=
===Balance FPGA resources while creating design partitions===
When creating circuit partitions, engineers should first observe the available resources the FPGA offers, since the design will be placed onto the FPGA fabric.<ref name="Aldec" /> The architecture of each FPGA is dependent on the manufacturer, but the main goal in design partitioning is to have an even balance of FPGA resource utilization. Various FPGA resources include [[
===Placing and routing partitions===
In order to achieve optimal place and routing for partitioned designs, the engineer must focus on FPGA pin count and inter-FPGA signals. After partitioning the design into separate FPGAs, the number of inter-FPGA signals must not to exceed the pin count on the FPGA.<ref>http://www.fpga-faq.com/FAQ_Pages/prototyping.pdf {{Bare URL PDF|date=March 2022}}</ref> This is very difficult to avoid when circuit designs are immense, thus signals must utilize strategies such as [[time-division multiplexing]] (TDM) which multiple signals can be transferred over a single line.<ref>{{Cite web|url=http://www.inetdaemon.com/tutorials/telecom/t-carrier/time-division_multiplexing.shtml|title=Time-Division Multiplexing|website=www.inetdaemon.com|language=en-US|access-date=2018-10-08}}</ref> These multiple signals, called sub-channels, take turns being transferred over the line over a time slot. When the TDM ratio is high, the bus clock frequency has to be reduced to accommodate time slots for each sub-channel. By reducing the clock frequency the throughput of the system is hindered.<ref name=Aldec/>
===Timing requirements===
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==Debugging==
One of the most difficult and time-consuming tasks in FPGA prototyping is debugging system designs. The term coined for this is "FPGA hell".<ref>{{Cite web|url=https://zipcpu.com/blog/2017/05/19/fpga-hell.html|title=FPGA Hell|website=zipcpu.com|access-date=2019-11-05}}</ref><ref>{{Cite web|url=http://www.rocketmanrc.com/downloads/MakerFaire2019FPGAsPresentation.pdf|title=Getting Started with FPGAs|last=|first=|date=|website=
A number of standard debugging tools are offered by FPGA vendors including ChipScope and SignalTAP. These tools can probe a maximum of 1024 signals and require extensive LUT and memory resources. For SoC and other designs, efficient debugging often requires concurrent access to 10,000 or more signals. If a bug is not able to be captured by the original set of probes, gaining access to additional signals results in a “go home for the day” situation. This is due to long and complex CAD flows for synthesis and place and route that can require from 8 to 18 hours to complete.
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Certus brings enhanced RTL-level visibility to FPGA-based debugging. It uses a highly efficient multi-stage concentrator as the basis for its observation network to reduce the number of LUTs required per signal to increase the number of signals that can be probed in a given space. The ability to view any combination of signals is unique to Certus and breaks through one of the most critical prototyping bottlenecks.<ref>{{cite web|url=http://www.tek.com/document/whitepaper/break-through-your-asic-prototyping-bottlenecks | title=Break Through Your ASIC Prototyping Bottlenecks| date= 2012-10-23|accessdate=2012-10-30}}</ref>
EXOSTIV uses large external storage and gigabit transceivers to extract deep traces from FPGA running at speed. The improvement lays in its ability to see large traces in time as a continuous stream or in bursts. This enables exploring extended debugging scenarios that can't be reached by traditional [[embedded instrumentation]] techniques. The solution claims saving both the FPGA I/O resources and the FPGA memory at the expense of gigabit transceivers, for an improvement of a factor of 100,000 and more on visibility.<ref>{{cite web|url=https://www.exostivlabs.com/why-exostiv/ | title=Why EXOSTIV?| date= 2015-10-14|accessdate=2015-11-25}}</ref><ref>{{cite web| url=https://www.exostivlabs.com/asic-soc-prototyping/
==See also==
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*FPGA Prototyping Solutions
**[http://www.s2cinc.com S2C Rapid Prototyping Solutions]
**[
**[http://www.proFPGA.com/ proFPGA Prototyping Boards]
**[http://www.hypersilicon.com/ HyperSilicon Prototyping Boards]
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