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{{short description|Digital signal generator}}
A '''numerically controlled oscillator''' ('''NCO''') is a digital [[signal generator]] which creates a [[Synchronous circuit|synchronous]] (i.e. clocked), discrete-time, discrete-valued representation of a [[waveform]], usually [[sinusoidal]].<ref name="IEEE">Jane Radatz, The IEEE Standard Dictionary of Electrical and Electronics Terms, IEEE Standards Office, New York, NY, 1997</ref> NCOs are often used in conjunction with a [[digital-to-analog converter]] (DAC) at the output to create a [[direct digital synthesizer]] (DDS).{{#tag:ref|While some authors use the terms DDS and NCO interchangeably,<ref name="latticeSC" /> by convention an NCO refers to the digital (i.e. the discrete-time, discrete amplitude) portion of a DDS<ref name="IEEE"/>}}▼
▲A '''numerically controlled oscillator''' ('''NCO''') is a digital [[signal generator]] which creates a [[Synchronous circuit|synchronous]] (i.e., clocked), discrete-time, discrete-valued representation of a [[waveform]], usually [[sinusoidal]].<ref name="IEEE">
==Operation==
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[[Image:Generic NCO.png|frame|Figure 1: Numerically controlled oscillator with optional quadrature output]]
When clocked, the phase accumulator (PA) creates a [[modulo operation|modulo]]-2<sup>N</sup> [[sawtooth wave]]form which is then converted by the phase-to-amplitude converter (PAC) to a sampled sinusoid, where N is the number of bits carried in the phase accumulator. N sets the NCO frequency resolution and is normally much larger than the number of bits defining the memory space of the PAC [[look-up table]]. If the PAC capacity is 2<sup>M</sup>, the PA output word must be truncated to M bits as shown in Figure 1. However, the truncated bits can be used for interpolation. The truncation of the phase output word does not affect the frequency accuracy but produces a time-varying periodic phase error which is a primary source of spurious products. Another spurious product generation mechanism is finite word length effects of the PAC output (amplitude) word.<ref name="kroupa">{{cite book |last=Kroupa
The frequency accuracy relative to the clock frequency is limited only by the precision of the arithmetic used to compute the phase.<ref name="kroupa"/> NCOs are phase- and frequency-agile, and can be trivially modified to produce a [[phase modulation|phase-modulated]] or [[frequency modulation|frequency-modulated]] output by summation at the appropriate node, or provide [[quadrature phase|quadrature]] outputs as shown in the figure.
==Phase accumulator==
<!-- linked from redirect [[Phase accumulator]] -->
A binary phase accumulator consists of an N-bit binary [[adder (electronics)|adder]] and a [[hardware register|register]] configured as shown in Figure 1.<ref name="Grzeg"/> Each clock cycle produces a new N-bit output consisting of the previous output obtained from the register summed with the frequency control word (FCW) which is constant for a given output frequency. The resulting output waveform is a staircase with step size <math>\Delta F</math>, the integer value of the FCW.<ref name="ADI"/> In some configurations, the phase output is taken from the output of the register which introduces a one clock cycle [[latency (engineering)|latency]] but allows the adder to operate at a higher clock rate.<ref name="latticeSC"
[[Image:Phase Accum Graph.png|frame|Figure 2: Normalized phase accumulator output]]
The adder is designed to overflow when the sum of the [[absolute value]] of its operands exceeds its capacity (2<sup>N</sup>−1). The overflow bit is discarded so the output word width is always equal to its input word width. The remainder <math>\phi _n</math>, called the residual, is stored in the register and the cycle repeats, starting this time from <math>\phi _n</math> (see figure 2).<ref name="Grzeg"/> Since a phase accumulator is a [[finite
:<math>\mbox{GRR}=\frac{2^N}{\mbox{GCD}(\Delta F,2^N)}</math>
where GCD is the [[greatest common divisor]] function. The GRR represents the true periodicity for a given <math>\Delta F</math> which for a high resolution NCO can be very long.<ref name="Grzeg"/> Usually we are more interested in the ''operating frequency'' determined by the average overflow rate, given by<ref name="ADI">{{citation |last1=Murphy |first1=Eva |last2=Slattery |first2=Colm |url=http://www.analog.com/library/analogdialogue/archives/38-08/dds.html |title=All About Direct Digital Synthesis |journal=Analog Dialogue |volume=38 |date=August 2004 |publisher=Analog Devices}}</ref>
:<math>F_{out} = \frac{\Delta F}{2^N}F_{clock} </math> (1)
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==Phase-to-amplitude converter==
The phase-amplitude converter creates the sample-___domain waveform from the truncated phase output word received from the PA. The PAC can be a simple [[read only memory]] containing 2<sup>M</sup> contiguous samples of the desired output waveform which typically is a sinusoid. Often though, various tricks are employed to reduce the amount of memory required. This include various trigonometric expansions,<ref>{{
==Spurious products==
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===Phase truncation spurs===
The number of phase accumulator bits of an NCO
:<math>n_W=\frac{2^W}{\mbox{GCD}(\Delta F,2^W)}-1</math> (3)
where W is the number of bits truncated.
In calculating the [[
:<math>\zeta _{max}=2^{-M} \frac{\pi \mbox{GCD}(\Delta F,2^W)}{\sin \left( \pi \cdot 2^{-P}\mbox{GCD}(\Delta F,2^W) \right)}</math>
where P is
:<math>\zeta _{max} \approx -6.02 \cdot P\;\mbox{dBc}.</math>
Another related spurious generation method is the slight modulation due to the GRR outlined above. The amplitude of these spurs is low for large N and their frequency is generally too low to be detectable but they may cause issues for some applications.<ref name="Grzeg"/>
One way to reduce the truncation in the address lookup is to have several smaller lookup tables in parallel and use the upper bits to index into the tables and the lower bits to weigh them for linear or quadratic interpolation. Ie use a 24-bit phase accumulator to look up into two 16-bit LUTS. Address into the truncated 16 MSBs, and that plus 1. Linearly interpolate using the 8 LSBs as weights. (One could instead use 3 LUTs instead and quadratically interpolate). This can result in decreased distortion for the same amount of memory at the cost of some multipliers.
===Amplitude truncation spurs===
Another source of spurious products is the amplitude [[Quantization (signal processing)|quantization]] of the sampled waveform contained in the PAC look up table(s). If the number of DAC bits is P, the
AM spur level is approximately equal to −6.02
===Mitigation techniques===
Phase truncation spurs can be reduced substantially by the introduction of [[White noise|white gaussian noise]] prior to truncation. The so-called [[dither]] noise is summed into the lower W+1 bits of the PA output word to linearize the truncation operation. Often the improvement can be achieved without penalty because the DAC noise floor tends to dominate system performance. Amplitude truncation spurs can not be mitigated in this fashion. Introduction of noise into the static values held in the PAC ROMs would not eliminate the cyclicality of the
==See also==
* [[Direct digital
* [[Digital-to-analog converter]] (DAC)▼
* [[Digitally controlled oscillator]] (DCO)
▲*[[Digital-to-analog converter]]
==References==
{{reflist
{{good article}}
{{DEFAULTSORT:Numerically
[[Category:Digital signal processing]]
[[Category:Synthesizers]]
[[Category:
[[Category:Digital electronics]]
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