Pipeline (computing): Difference between revisions

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=== Buffering ===

Under ideal circumstances, if all processing elements are synchronized and take the same amount of time to process, then each item can be received by each element just as it is released by the previous one, in a single [[clock (computing)|clockcycle]] cycle. That way, the items will flow through the pipeline at a constant speed, like waves in a water channel. In such "wave pipelines",<ref>{{cite book |author1=O. Hauck |author2=Sorin A. Huss |author3=M. Garg |title=Proceedings. Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems |chapter=Two-phase asynchronous wave-pipelines and their application to a 2D-DCT |year=1999 |pages=219–228 |doi=10.1109/ASYNC.1999.761536 |isbn=0-7695-0031-5 |s2cid=206515615 }}</ref> no synchronization or buffering is needed between the stages, besides the storage needed for the data items.

More generally, buffering between the pipeline stages is necessary when the processing times are irregular, or when items may be created or destroyed along the pipeline. For example, in a graphics pipeline that processes triangles to be rendered on the screen, an element that checks the visibility of each triangle may discard the triangle if it is invisible, or may output two or more triangular pieces of the element if they are partly hidden. Buffering is also needed to accommodate irregularities in the rates at which the application feeds items to the first stage and consumes the output of the last one.