Compressed instruction set: Difference between revisions

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==Concept==

[[Microprocessor]]s encode their instructions as a series of [[bit]]s, normally divided into a number of 8-bit [[byte]]s. For instance, in the [[MOS 6502]], the {{code|ADC}} instruction performs binary addition between an operand value and the value already stored in the [[Accumulator (computing)|accumulator]]. There are a variety of places the processor might find the operand; it might be located in [[main memory]], or in the special [[zero page]], or be an explicit constant like "10". Each of these variations used a different 8-bit instruction, or [[opcode]]; if one wanted to add the constant 10 to the accumulator the instruction would be encoded in memory as {{code|$69 $0A}}, with $0A being [[hexadecimal]] for the decimal value 10. If it was instead adding the value stored in main memory at ___location $4400, it would be {{code|$6D $004400 $44}}, with a [[Endianness|little-endian]] address.{{sfn|Verts|2004}}

Note that the second instruction requires three bytes because the memory address is 16 bits long. Depending on the instruction, it might use one, two, or three bytes.{{sfn|Verts|2004}} This is now known as a [[variable length instruction set]], although that term was not common at the time as most processors, including [[mainframe]]s and [[minicomputer]]s, normally used some variation of this concept. Even in the late 1970s, as microprocessors began to move from 8-bit formats to 16, this concept remained common; the [[Intel 80888086]] continued to use 8-bit opcodes which could be followed by zero to sixfive additional bytes depending on the [[addressing mode]].<ref>{{cite magazine |title=Understanding ARM Architectures |url=https://www.informit.com/articles/article.aspx?p=1620207&seqNum=3 |date=23 August 2010 |website=informIT}}</ref>

It was during the move to 32-bit systems, and especially as the [[RISC]] concept began to take over processor design, that variable length instructions began to go away. In the [[MIPS architecture]], for instance, all instructions are a single 32-bit value, with a 6-bit opcode in the [[most significant bit]]s and the remaining 26 bits used in various ways representing its limited set of addressing modes. Most RISC designs are similar. Moving to a fixed-length instruction format was one of the key design concepts behind the performance of early RISC designs; in earlier systems the instruction might take one to six memory cycles to read, requiring wiring between various parts of the logic to ensure the processor didn't attempt to perform the instruction before the data was ready. In RISC designs, operations normally take one cycle, greatly simplifying the decoding. The savings in these interlocking circuits is instead applied to additional logic or adding [[processor register]]s, which have a direct impact on performance.<ref>{{cite web |url=http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s07.html |title=MIPS Instruction Code Formats |website=Computer Science 315 Lecture Notes |first=Jason |last=Bacon |access-date=2021-04-09 |archive-date=2019-07-17 |archive-url=https://web.archive.org/web/20190717133605/http://www.cs.uwm.edu/classes/cs315/Bacon/Lecture/HTML/ch05s07.html |url-status=dead }}</ref>

===Code density===

The downside to the RISC approach is that many instructions simply do not require four bytes. For instance, the [[Logical shift|Logical Shift Left]] instruction shifts the bits in a register to the left. In the 6502, which has only a single arithmetic register A, this instruction can be represented entirely by its 8-bit opcode {{code|$06}}.{{sfn|Verts|2004}} On processors with more registers, all that is needed is the opcode and register number, another 4 or 5 bits. On MIPS, for instance, the instruction needs only a 6-bit opcode and a 5-bit register number. But as is the case for most RISC designs, the instruction still takes up a full 32 bits. As these sorts of instructions are relatively common, RISC programs generally take up more memory than the same program on a variable length processor.{{sfn|Weaver|McKee|2009}}

One notable, and particularly early, exception amongst RISC designs is the [[IBM 801]] architecture which maintains five instruction formats: two utilising a 16-bit instruction length, and three utilising a 32-bit instruction length.<ref name="ibm_801_system_architecture">{{ cite book | url=http://bitsavers.org/pdf/ibm/system801/System_801_Principles_of_Operation_Jan76.pdf | title=System 801 Principles of Operation | publisher=International Business Machines | date=16 January 1976 | access-date=11 November 2024 }}</ref>{{rp|pages=10}} For instructions requiring less space, such as shift instructions employing only register operands, the shorter 16-bit instruction formats are used.<ref name="ibm_801_system_architecture"/>{{rp|pages=51–58}}

In the 1980s, when the RISC concept was first emerging, this was a common point of complaint. As the instructions took up more room, the system would have to spend more time reading instructions from memory. It was suggested these extra accesses might actually slow the program down. Extensive [[benchmarking]] eventually demonstrated RISC was faster in almost all cases, and this argument faded. However, there are cases where memory use remains a concern regardless of performance, and that is in small systems and embedded applications. Even in the early 2000s, the price of [[DRAM]] was enough that cost-sensitive devices had limited memory. It was for this market that [[Hitachi]] developed the [[SuperH]] design.<ref>{{cite web |url=http://resource.renesas.com/lib/eng/e_learnig/sh4/02/index.html |title=Effects of 16-bit instructions |website=Renesas}}</ref>

In the 1980s, when the RISC concept was first emerging, thisincreased program size was a common point of complaint. As the instructions took up more room, the system would have to spend more time reading instructions from memory. It was suggested these extra accesses might actually slow the program down. Extensive [[benchmarking]] eventually demonstrated RISC was faster in almost all cases, and this argument faded. However, there are cases where memory use remains a concern regardless of performance, and that is in small systems and embedded applications. Even in the early 2000s, the price of [[DRAM]] was enough that cost-sensitive devices had limited memory. It was for this market that [[Hitachi]] developed the [[SuperH]] design.<ref>{{cite web |url=http://resource.renesas.com/lib/eng/e_learnig/sh4/02/index.html |title=Effects of 16-bit instructions |website=Renesas}}</ref>

In the earlier SuperH designs, SH-1 through SH-4, instructions always take up 16 bits. The resulting instruction set has real-world limitations; for instance, it can only perform two-operand math of the form {{code|A {{=}} A + B}}, whereas most processors of the era used the three-operand format, {{code|A {{=}} B + C}}. By removing one operand, four bits are removed from the instruction (there are 16 registers, needing 4 bits), although this is at the cost of making math code somewhat more complex to write. For the markets targeted by the SuperH, this was an easy tradeoff to make. A significant advantage of the 16-bit format is that the [[instruction cache]] now holds twice as many instructions for any given amount of [[Static random-access memory|SRAM]]. This allows the system to perform at higher speeds, although some of that might be mitigated by the use of additional instructions needed to perform operations that might be performed by a single 3-operand instruction.{{sfn|SuperH|1996}}