Deep reactive-ion etching: Difference between revisions

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{{Short description|Highly anisotropic etch process}}

'''Deep Reactive Ion Etching''' or '''DRIE''' is a highly [[anisotropic]] [[etching|etch]] process developed in the [[semiconductor]] industry and used to create deep and high [[aspect ratio]] channels in materials such as [[silicon]]. Widely used for [[MEMS]] and high value integrated [[capacitor]]s, channels with vertical sides and having [[aspect ratio]]s greater than 20:1 can be produced.

{{More citations needed|date=December 2009}}

'''Deep reactive-ion etching''' ('''DRIE''') is a special subclass of [[reactive-ion etching]] (RIE). It enables highly [[anisotropy|anisotropic]] [[etching (microfab)|etch]] process used to create deep penetration, steep-sided holes and trenches in [[wafer (semiconductor)|wafer]]s/substrates, typically with high [[aspect ratio (image)|aspect ratio]]s. It was developed for [[microelectromechanical systems]] (MEMS), which require these features, but is also used to excavate trenches for high-density [[capacitor]]s for [[dynamic random access memory|DRAM]] and more recently for creating through-silicon vias ([[Through-silicon via|TSVs]]) in advanced 3D wafer level packaging technology.

In DRIE, the substrate is placed inside a reactor, and several gases are introduced. A plasma is struck in the gas mixture which breaks the gas molecules into ions. The ions are accelerated towards, and react with the surface of the material being etched, forming another gaseous element. This is known as the chemical part of the reactive ion etching. There is also a physical part, if ions have enough energy, they can knock atoms out of the material to be etched without chemical reaction.

There are three primary processes which are brought together to achieve the results in DRIE. First a highly reactive gas is used to perform an [[isotropic]] etch of the [[substrate]]. After a brief period the etching is stopped and the process switches over to deposition of a layer of [[passivation]] over the whole surface. This protects the substrate from further chemical attack and prevents further etching. The process now returns to etching, which is where the third process comes into play. Within the chamber there is an energetic [[plasma]] which produces a [[collimated]] stream of [[ion]]s that bombard the substrate. By a process of [[sputtering]] these ions remove the passivation from the bottom of the previous etch step, but not from the sides. The etchant chemicals can then erode only the bottom of the channels.

There are two main technologies for high-rate DRIE: cryogenic and Bosch, although the Bosch process is the only recognised production technique. Both Bosch and cryogenic processes can fabricate 90° (truly vertical) walls, but often the walls are slightly tapered, e.g. 88° ("reentrant") or 92° ("retrograde").

The process is repeated many times over resulting in a large number of very small [[isotropic]] etch steps taking place only at the bottom of the etched pits. It is this selectivity that leads to the overall anisotropy of the process and the creation of high aspect ratio channels with vertical sidewalls.

Another mechanism is sidewall passivation: SiO_xF_y [[functional group]]s (which originate from sulphur hexafluoride and oxygen etch gases) condense on the sidewalls, and protect them from lateral etching. As a combination of these processes, deep vertical structures can be made.

[[category:semiconductors]]

==Cryogenic process==

In cryogenic-DRIE, the wafer is chilled to −110 °C (163 [[kelvin|K]]). The low temperature slows down the [[chemical reaction]] that produces isotropic etching. However, [[ion]]s continue to bombard upward-facing surfaces and etch them away. This process produces trenches with highly vertical sidewalls. The primary issues with cryo-DRIE is that the standard masks on substrates crack under the extreme cold, plus etch by-products have a tendency of depositing on the nearest cold surface, i.e. the substrate or electrode.

==Bosch process==

[[File:Bosch process PILLAR.jpg|thumb|alt=A silicon pillar fabricated using the Bosch process|A silicon micro-pillar fabricated using the Bosch process]]

The Bosch process, named after the German company [[Robert Bosch GmbH]] which patented the process,<ref>[http://www.freepatentsonline.com/5501893.html Basic Bosch process patent application]</ref><ref>[http://www.freepatentsonline.com/6531068.html Improved Bosch process patent application]</ref><ref>[http://www.freepatentsonline.com/6284148.html Bosch process "Parameter Ramping" patent application]</ref><ref>[https://patents.google.com/patent/US5501893A Method of anisotropically etching silicon]</ref><ref>[https://patents.google.com/patent/US6284148B1 Method for anisotropic etching of silicon]</ref><ref>[https://patents.google.com/patent/US6531068B2 Method of anisotropic etching of silicon]</ref> also known as pulsed or time-multiplexed etching, alternates repeatedly between two modes to achieve nearly vertical structures:

# A standard, nearly [[isotropy|isotropic]] [[plasma etch]]. The plasma contains some ions, which attack the wafer from a nearly vertical direction. [[Sulfur hexafluoride]] [SF₆] is often used for [[silicon]].

# Deposition of a chemically inert [[Passivation (chemistry)|passivation]] layer. (For instance, [[Octafluorocyclobutane]] [C₄F₈] source gas yields a substance similar to [[Teflon]].)

[[File:Bosch process sidewall.jpg|thumb|alt=Undulating sidewall as a result of the Bosch process|Undulating sidewall of a silicon structure created using the Bosch process]]

Each phase lasts for several seconds. The passivation layer protects the entire substrate from further chemical attack and prevents further etching. However, during the etching phase, the directional [[ion]]s that bombard the substrate attack the passivation layer at the bottom of the trench (but not along the sides). They collide with it and [[sputter]] it off, exposing the substrate to the chemical etchant.

These etch/deposit steps are repeated many times over resulting in a large number of very small [[isotropic]] etch steps taking place only at the bottom of the etched pits. To etch through a 0.5&nbsp;mm silicon wafer, for example, 100–1000 etch/deposit steps are needed. The two-phase process causes the sidewalls to undulate with an amplitude of about 100–500 [[nanometre|nm]]. The cycle time can be adjusted: short cycles yield smoother walls, and long cycles yield a higher etch rate.

==Applications==

Etching depth typically depends on the application:

* in [[DRAM]] memory circuits, capacitor trenches may be 10–20&nbsp;μm deep,

* in MEMS, DRIE is used for anything from a few micrometers to 0.5&nbsp;mm.

* in irregular chip dicing, DRIE is used with a novel hybrid soft/hard mask to achieve sub-millimeter etching to dice silicon dies into lego-like pieces with irregular shapes.<ref>{{cite journal | last1= Ghoneim | first1= Mohamed | last2 = Hussain | first2= Muhammad | title = Highly Manufacturable Deep (Sub-Millimeter) Etching Enabled High Aspect Ratio Complex Geometry Lego-Like Silicon Electronics| journal= Small | date= 1 February 2017 | doi=10.1002/smll.201601801 | pmid= 28145623 | volume=13 | issue= 16 | page=1601801| hdl= 10754/622865 | url= https://repository.kaust.edu.sa/bitstream/10754/622865/1/smll.201601801_R2.pdf | hdl-access= free }}</ref><ref>{{cite news | last= Mendis | first= Lakshini | title= Lego-like Electronics | newspaper= Nature Middle East | date= 14 February 2017 | doi= 10.1038/nmiddleeast.2017.34 }}</ref><ref>{{cite news | last= Berger | first= Michael | title=Lego like silicon electronics fabricated with hybrid etching masks | newspaper= Nanowerk | date= 6 February 2017 | url= http://www.nanowerk.com/spotlight/spotid=45763.php}}</ref>

* in flexible electronics, DRIE is used to make traditional monolithic CMOS devices flexible by reducing the thickness of silicon substrates to few to tens of micrometers.<ref>{{ cite journal | last1= Ghoneim | first1= Mohamed | first2=Nasir | last2=Alfaraj | first3=Galo | last3=Torres-Sevilla | first4=Hossain | last4=Fahad | first5=Muhammad | last5=Hussain | title=Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS | journal=IEEE Transactions on Electron Devices | volume= 63 | issue= 7 | pages= 2657–2664 | date= July 2016 | doi=10.1109/ted.2016.2561239| hdl= 10754/610712 | bibcode= 2016ITED...63.2657G | s2cid= 26592108 | url= https://figshare.com/articles/journal_contribution/5048395 | hdl-access=free }}</ref><ref>{{ cite journal | first1= Mohamed T. | last1= Ghoneim | first2= Muhammad M. | last2= Hussain | title=Review on physically flexible nonvolatile memory for internet of everything electronics | journal= Electronics | volume= 4 | issue= 3 | pages= 424–479 | date=23 July 2015 | arxiv= 1606.08404 | doi= 10.3390/electronics4030424 | s2cid= 666307 | doi-access= free }}</ref><ref>{{cite journal | first1= Mohamed T. | last1= Ghoneim | first2= Muhammad M. | last2= Hussain | title=Study of harsh environment operation of flexible ferroelectric memory integrated with PZT and silicon fabric | journal=Applied Physics Letters | date=3 August 2015 | doi=10.1063/1.4927913 | volume=107 | issue= 5 | page=052904| hdl= 10754/565819 | url=https://repository.kaust.edu.sa/bitstream/10754/565819/1/1.4927913.pdf | bibcode= 2015ApPhL.107e2904G | hdl-access=free }}</ref><ref>{{cite journal | first1=Mohamed T. | last1=Ghoneim | first2=Jhonathan P. | last2=Rojas | first3=Chadwin D. | last3=Young | first4=Gennadi | last4=Bersuker | first5=Muhammad M. | last5=Hussain | title=Electrical Analysis of High Dielectric Constant Insulator and Metal Gate Metal Oxide Semiconductor Capacitors on Flexible Bulk Mono-Crystalline Silicon | journal= IEEE Transactions on Reliability | volume=64 | issue=2 | pages=579–585 | date=26 November 2014 | doi=10.1109/TR.2014.2371054 | s2cid=11483790 | url=https://figshare.com/articles/journal_contribution/5048398 }}</ref><ref>{{cite journal | first1=Mohamed T. | last1=Ghoneim | first2=Mohammed A. | last2=Zidan | first3=Mohammed Y. | last3=Alnassar | first4=Amir N. | last4=Hanna | first5=Jurgen | last5= Kosel | first6=Khaled N. | last6=Salama | first7=Muhammad | last7=Hussain | title=Flexible Electronics: Thin PZT-Based Ferroelectric Capacitors on Flexible Silicon for Nonvolatile Memory Applications | journal=Advanced Electronic Materials | date=15 June 2015 | doi=10.1002/aelm.201500045 | volume=1 | issue=6 | page=1500045| doi-access=free | s2cid=110038210 | url=https://figshare.com/articles/journal_contribution/5048353 }}</ref><ref>{{cite journal | first1=Mohamed T. | last1=Ghoneim |first2=Arwa | last2=Kutbee | first3=Farzan | last3=Ghodsi | first4=G. |last4=Bersuker | first5=Muhammad M. | last5=Hussain | title=Mechanical anomaly impact on metal–oxide–semiconductor capacitors on flexible silicon fabric | journal= Applied Physics Letters | date=9 June 2014 | doi=10.1063/1.4882647 | volume=104 | issue=23 | page=234104| hdl=10754/552155 | url=http://repository.kaust.edu.sa/kaust/bitstream/10754/552155/1/1.4882647.pdf | bibcode=2014ApPhL.104w4104G | s2cid=36842010 | hdl-access=free }}</ref>

DRIE is distinguished from RIE by its etch depth. Practical etch depths for RIE (as used in [[integrated circuit|IC]] manufacturing) would be limited to around 10&nbsp;μm at a rate up to 1&nbsp;μm/min, while DRIE can etch features much greater, up to 600&nbsp;μm or more with rates up to 20&nbsp;μm/min or more in some applications.

DRIE of glass requires high plasma power, which makes it difficult to find suitable mask materials for truly deep etching. Polysilicon and nickel are used for 10–50&nbsp;μm etched depths. In DRIE of polymers, Bosch process with alternating steps of SF₆ etching and C₄F₈ passivation take place. Metal masks can be used, however they are expensive to use since several additional photo and deposition steps are always required. Metal masks are not necessary however on various substrates (Si [up to 800&nbsp;μm], InP [up to 40&nbsp;μm] or glass [up to 12&nbsp;μm]) if using chemically amplified negative resists.

Gallium ion implantation can be used as etch mask in cryo-DRIE. Combined nanofabrication process of focused ion beam and cryo-DRIE was first reported by N Chekurov ''et al'' in their article "The fabrication of silicon nanostructures by local gallium implantation and cryogenic deep reactive ion etching".<ref>{{cite journal |last1=Chekurov |first1=N |last2=Grigoras |first2=K |last3=Peltonen |first3=A |last4=Franssila |first4=S |last5=Tittonen |first5=I |display-authors=2 |title=The fabrication of silicon nanostructures by local gallium implantation and cryogenic deep reactive ion etching |journal=Nanotechnology |date=11 February 2009 |volume=20 |issue=6 |pages=065307 |doi=10.1088/0957-4484/20/6/065307 |pmid=19417383 |bibcode=2009Nanot..20f5307C |s2cid=9717001 |url=https://www.researchgate.net/publication/24403592}}</ref>

===Precision machinery===

DRIE has enabled the use of silicon mechanical components in high-end wristwatches. According to an engineer at [[Cartier (jeweler)|Cartier]], “There is no limit to geometric shapes with DRIE,”.<ref>{{cite news | last = Kolesnikov-Jessop | first = Sonia | title = Precise Future of Silicon Parts Still Being Debated | newspaper = The New York Times | ___location = New York | date = 23 November 2012 | url = https://www.nytimes.com/2012/11/24/fashion/24iht-acaw2-silicon24.html }}</ref> With DRIE it is possible to obtain an [[aspect ratio]] of 30 or more,<ref>{{cite journal | last1=Yeom | first1=Junghoon | last2=Wu | first2=Yan | last3=Selby | first3=John C. | last4=Shannon | first4=Mark A. | title=Maximum achievable aspect ratio in deep reactive ion etching of silicon due to aspect ratio dependent transport and the microloading effect | journal=Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures | publisher=American Vacuum Society | volume=23 | issue=6 | year=2005 | issn=0734-211X | doi=10.1116/1.2101678 | page=2319| bibcode=2005JVSTB..23.2319Y }}</ref> meaning that a surface can be etched with a vertical-walled trench 30 times deeper than its width.

This has allowed for silicon components to be substituted for some parts which are usually made of steel, such as the [[hairspring]]. Silicon is lighter and harder than steel, which carries benefits but makes the manufacturing process more challenging.

==See also==

*[[Microelectromechanical systems]]

==References==

<references />

{{Bosch}}

{{DEFAULTSORT:Deep Reactive-Ion Etching}}

[[Category:Semiconductor device fabrication]]

[[Category:Microtechnology]]

[[Category:Etching (microfabrication)]]