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{{Use American English|date = April 2019}}
{{missing information||three [[OpenPOWER]] cores, one Moxie core, both at RTL level|date=July 2020}}
A '''soft microprocessor''' (also called softcore microprocessor or a '''soft processor''') is a [[microprocessor]] core that can be wholly implemented using [[logic synthesis]]. It can be implemented via different [[semiconductor]] devices containing programmable logic (e.g.
▲{{Short description|microprocessor design embeddable in other computer systems}}
▲A '''soft microprocessor''' (also called softcore microprocessor or a '''soft processor''') is a [[microprocessor]] core that can be wholly implemented using [[logic synthesis]]. It can be implemented via different [[semiconductor]] devices containing programmable logic (e.g., [[Application-specific integrated circuit|ASIC]], [[Field-programmable gate array|FPGA]], [[Complex programmable logic device|CPLD]]), including both high-end and commodity variations.<ref>http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html {{Webarchive|url=https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html |date=2018-10-13 }}
"Zet soft core running Windows 3.0" by Andrew Felch 2011</ref>
Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.<ref>
{{cite web |url=http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615 |title=
"FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006
</ref> In those [[multi-core]] systems, rarely used resources can be shared between all the cores in a cluster.
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</ref> This is one way to implement [[Massively parallel|massive parallelism]] in computing and can likewise be applied to [[In-memory processing|in-memory computing]].
A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.<ref>{{Cite web
| author=Joe DeLaere.
| title="Top 7 Reasons to Replace Your Microcontroller with a MAX 10 FPGA" </ref><ref>{{Cite web
|author1=John Swan
| title="Using FPGAs to avoid microprocessor obsolescence" | date=2008
| archive-url=https://web.archive.org/web/20161013004106/http://www.embedded.com/print/4015159
</ref><ref>▼
| archive-date=2016-10-13
▲}}</ref><ref>
{{Cite web|url=https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/|title=FPGA processor IP needs to be supported|last=Staff|date=2010-02-03|website=Electronics Weekly|language=en-GB|access-date=2019-04-03}}
</ref>
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| [http://opencores.org/project,pavr Project page at Opencores]
| VHDL
|-
| softavrcore
| Andras Pal
| {{yes}}
| Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM)
| [[Atmel AVR]]-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included
| [http://opencores.org/project/softavrcore Project page at Opencores]
| Verilog
|-
| colspan="7" align="center" | ''based on the [[MicroBlaze]] instruction set architecture''
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| SystemVerilog
|-
|
| Zeus Gómez Marmolejo
| {{yes}}
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|
| 9-bit RISC, very small size, C-programmable
| [http://www.entner-electronics.com/tl/index.php/eric5.html ERIC5] {{Webarchive|url=https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html |date=2016-03-05 }}
| VHDL
|-
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| {{yes}}
| [[Wishbone (computer bus)|Wishbone]], B4/pipelined
| 32-bit RISC/Vector CPU implementing the
| [https://mrisc32.bitsnbites.eu/ MRISC32]
| VHDL
| |||