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{{Short description|Microprocessor design embeddable in other computer systems}}
{{Use American English|date = April 2019}}
{{missing information||three [[OpenPOWER]] cores, one Moxie core, both at RTL level|date=July 2020}}
A '''soft microprocessor''' (also called softcore microprocessor or a '''soft processor''') is a [[microprocessor]] core that can be wholly implemented using [[logic synthesis]]. It can be implemented via different [[semiconductor]] devices containing programmable logic (e.g., [[Field-programmable gate array|FPGA]], [[Complex programmable logic device|CPLD]]), including both high-end and commodity variations.<ref>{{usurped|1=[https://web.archive.org/web/20181013095941/http://www.dailycircuitry.com/2011/10/zet-soft-core-running-windows-30.html Article title]}}
"Zet soft core running Windows 3.0" by Andrew Felch 2011</ref>
Most systems, if they use a soft processor at all, only use a single soft processor. However, a few designers tile as many soft cores onto an FPGA as will fit.<ref>
{{cite web |url=http://www.embedded.com/columns/showArticle.jhtml?articleID=192700615 |title=
"FPGA Architectures from 'A' to 'Z'" by Clive Maxfield 2006
</ref> In those [[multi-core]] systems, rarely used resources can be shared between all the cores in a cluster.
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</ref> This is one way to implement [[Massively parallel|massive parallelism]] in computing and can likewise be applied to [[In-memory processing|in-memory computing]].
A soft microprocessor and its surrounding peripherals implemented in a FPGA is less vulnerable to obsolescence than a discrete processor.<ref>{{Cite web
| author=Joe DeLaere.
| title="Top 7 Reasons to Replace Your Microcontroller with a MAX 10 FPGA" </ref><ref>{{Cite web
|author1=John Swan
| title="Using FPGAs to avoid microprocessor obsolescence" | date=2008
| archive-url=https://web.archive.org/web/20161013004106/http://www.embedded.com/print/4015159
| archive-date=2016-10-13
}}</ref><ref>
{{Cite web|url=https://www.electronicsweekly.com/news/products/fpga-news/fpga-processor-ip-needs-to-be-supported-2010-02/|title=FPGA processor IP needs to be supported|last=Staff|date=2010-02-03|website=Electronics Weekly|language=en-GB|access-date=2019-04-03}}
</ref>
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| [http://opencores.org/project,pavr Project page at Opencores]
| VHDL
|-
| softavrcore
| Andras Pal
| {{yes}}
| Standard AVR buses (core-coupled I/O, synchronous SRAM, synchronous program ROM)
| [[Atmel AVR]]-compatible 8-bit RISC (up to AVR5), peripherals and SoC features included
| [http://opencores.org/project/softavrcore Project page at Opencores]
| Verilog
|-
| colspan="7" align="center" | ''based on the [[MicroBlaze]] instruction set architecture''
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| OPB, FSL
| Binary compatible with the MicroBlaze
| [https://web.archive.org/web/20090724052731/http://www.ccm.ece.vt.edu/~scraven/openfire.html]<ref>{{Cite web|url=http://opencores.org/project,openfire_core,overview|title=Overview :: OpenFire Processor Core :: OpenCores}}</ref>
| Verilog
|-
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| [[University of Cambridge]]
| {{yes|BSD}}
|
| [[MIPS architecture|MIPS]]
| [http://www.cl.cam.ac.uk/research/security/ctsrd/beri/ Project page]
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| Pablo Bleyer
| {{yes}}
|
| Compatible with the PicoBlaze processors
| [http://bleyer.org/pacoblaze PacoBlaze]
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| 32-bit, RISC-V / MIPS ISA subsets (retargetable), GCC toolchain
| [https://github.com/f32c/f32c f32c]
| VHDL
|-
| [https://github.com/stnolting/neorv32 NEORV32]
| Stephan Nolting
| {{yes|BSD}}
| Wishbone b4, AXI4
| rv32[i/e] [m] [a] [c] [b] [u] [Zfinx] [Zicsr] [Zifencei], RISC-V-compliant, CPU & SoC available, highly customizable, GCC toolchain
| [https://github.com/stnolting/neorv32 GitHub] [https://opencores.org/projects/neorv32 OpenCores]
| VHDL
|-
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| {{Yes}}
|
| [[Manycore processor|Manycore]] [[SPARC|SPARC V9]]
| [http://parallel.princeton.edu/openpiton/specs.html OpenPiton]
| Verilog
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| HT-Lab
| {{yes}}
|
| 8088-compatible CPU in VHDL
| [http://www.ht-lab.com/cpu86.htm cpu86]
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| SystemVerilog
|-
|
| Zeus Gómez Marmolejo
| {{yes}}
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| i486 SX compatible core
| [https://github.com/alfikpl/ao486 ao486]
| Verilog
|-
| colspan="7" align="center" | ''based on the [[Power ISA|PowerPC/Power]] instruction set architecture''
|-
| [[PowerPC 400#PowerPC 405|PowerPC 405S]]
| IBM
| {{No}}
| [[CoreConnect]]
| 32-bit PowerPC v.2.03 Book E
| [[IBM]]
| Verilog
|-
| [[PowerPC 400#PowerPC 440|PowerPC 440S]]
| IBM
| {{No}}
| [[CoreConnect]]
| 32-bit PowerPC v.2.03 Book E
| [[IBM]]
| Verilog
|-
| [[PowerPC 400#PowerPC 470|PowerPC 470S]]
| IBM
| {{No}}
| [[CoreConnect]]
| 32-bit PowerPC v.2.05 Book E
| [[IBM]]
| Verilog
|-
| [[OpenPower Microwatt|Microwatt]]
| IBM/OpenPOWER
| {{yes|CC-BY 4.0}}
| [[Wishbone (computer bus)|Wishbone]]
| 64-bit PowerISA 3.0 proof of concept
| [https://github.com/antonblanchard/microwatt Microwatt @ Github]
| VHDL
|-
| [[OpenPower Microwatt#Chiselwatt|Chiselwatt]]
| IBM/OpenPOWER
| {{yes|CC-BY 4.0}}
| [[Wishbone (computer bus)|Wishbone]]
| 64-bit PowerISA 3.0
| [https://github.com/antonblanchard/chiselwatt Chiselwatt @ Github]
| Chisel
|-
| [[Libre-SOC]]
| [https://libre-soc.org Libre-SoC.org]
| {{yes|BSD/LGPLv2+}}
| [[Wishbone (computer bus)|Wishbone]]
| 64-bit PowerISA 3.0. CPU/GPU/VPU implementation and custom vector instructions
| [https://libre-soc.org Libre-SoC.org]
| python/nMigen
|-
| [[IBM A2#A2I|A2I]]
| IBM/OpenPOWER
| {{yes|CC-BY 4.0}}
| Custom PBus
| 64-bit PowerPC 2.6 Book E. In order core
| [https://github.com/openpower-cores/a2i A2I @ Github]
| VHDL
|-
| [[IBM A2#A2O|A2O]]
| IBM/OpenPOWER
| {{yes|CC-BY 4.0}}
| Custom PBus
| 64-bit PowerPC 2.7 Book E. Out of order core
| [https://github.com/openpower-cores/a2o A2O @ Github]
| Verilog
|-
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| [[Synopsys#ARC International|ARC International]], [[Synopsys]]
| {{no}}
|
| 16/32/64-bit ISA RISC
| [
| Verilog
|-
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| Entner Electronics
| {{no}}
|
| 9-bit RISC, very small size, C-programmable
| [http://www.entner-electronics.com/tl/index.php/eric5.html ERIC5] {{Webarchive|url=https://web.archive.org/web/20160305131214/http://www.entner-electronics.com/tl/index.php/eric5.html |date=2016-03-05 }}
| VHDL
|-
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| {{yes}}
| [[Wishbone (computer bus)|Wishbone]], B4/pipelined
| 32-bit RISC/Vector CPU
| [https://mrisc32.bitsnbites.eu/ MRISC32]
| VHDL
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| TU Darmstadt / TU Dresden
| {{Yes}}
| Custom ([[Advanced eXtensible Interface|AXI]] support in development)
| 18-bit ISA (GNU Binutils / GCC support in development)
| [http://www.spartanmc.de SpartanMC]
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| Miguel Angel Ajo Pelayo
| {{yes|MIT}}
|
| PIC12F compatible, program synthesised in gates
| [http://projects.nbee.es/display/IPCORES/SYNPIC12+8bit+RISC+CPU+core nbee.es]
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| Verilog
|-
| [[
| Zylin AS
| {{yes}}
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| [http://opensource.zylin.com/zpu.htm Zylin CPU]
| VHDL
|-
|RISC5
|Niklaus Wirth| Niklaus Wirth
| {{yes}}
|Custom
|Running a complete graphical Oberon System including an editor and compiler. Software can be developed and ran on the same FPGA board.
|[http://www.projectoberon.com/ www.projectoberon.com/]
|Verilog
|}
== See also ==
* [[System on a chip|System-on-a-chip]] (SoC)
** [[Network on a chip|Network-on-a-chip]] (NoC)
* [[Reconfigurable computing]]
** [[Field-programmable gate array]] (FPGA)
* [[VHDL]]
* [[Verilog]]
** [[SystemVerilog]]
* [[Hardware acceleration]]
==References==
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