Digital signal processor: Difference between revisions

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{{shortShort description|Specialized microprocessor optimized for digital signal processing}}

[[File:Digital Signal Processor 9997.jpg|thumb|An L7A1045 DSP chip, as used in several [[Sampler (musical instrument)#Akai|Akai samplers]] and the [[Hyper Neo Geo 64]] arcade board]]

[[File:Dsp chip.jpg|right|thumb|A [[Texas Instruments TMS320|TMS320]] digital signal processor chip found in a [[Effects unit|guitar effects unit]]. A [[crystal oscillator]] may be seen above.]]

[[File:NeXTcube motherboard.jpg|thumb|The [[NeXTcube]] from 1990 had a [[Motorola 68040]] (25  MHz) and a digital signal processor [[Motorola 56001]] with 25  MHz which was directly accessible via an interface.]]

A '''digital signal processor''' ('''DSP''') is a specialized [[microprocessor]] chip, with its architecture optimized for the operational needs of [[digital signal processing]].<ref>{{ cite book | editor-last1 = Yovits | editor-first1 = Marshall C. | last1 = Dyer | first1 = Stephen A. | last2 = Harms | first2 = Brian K. | chapter = Digital Signal Processing | title = Advances in Computers | date = 1993-08-13 | volume = 37 | pages = 59{{hyphen}}118 | publisher = [[Academic Press]] | doi = 10.1016/S0065-2458(08)60403-9 | isbn = 978-0120121373 | issn = 0065-2458 | lccn = 59015761 | chapter-url = https://books.google.com/books?id=vL-bB7GALAwC&pg=PA104 | ol = OL10070096M | oclc = 858439915 | df = dmy-all}}</ref>{{rp|pages=104{{hyphen}}107}}<ref name="Liptak">{{ cite book | last = Liptak | first = B. G. | title = Process Control and Optimization | series = Instrument Engineers' Handbook | edition = 4th | year = 2006 | volume = 2 | pages = 11–12 | publisher = CRC Press | isbn = 978-0849310812 | url = https://books.google.com/books?id=TxKynbyaIAMC&pg=PA11 | via = [[Google Books]] }}</ref> DSPs are [[semiconductor device fabrication|fabricated]] on [[Integrated circuit|MOS integrated circuit]] chips.<ref name="computerhistory1979">{{cite web |title=1979: Single Chip Digital Signal Processor Introduced |url=https://www.computerhistory.org/siliconengine/single-chip-digital-signal-processor-introduced/ |access-date=14 October 2019 |website=The Silicon Engine |publisher=[[Computer History Museum]]}}</ref><ref name="edn">{{cite web |last1=Taranovich |first1=Steve |date=August 27, 2012 |title=30 years of DSP: From a child's toy to 4G and beyond |url=https://www.edn.com/design/systems-design/4394792/30-years-of-DSP--From-a-child-s-toy-to-4G-and-beyond |access-date=14 October 2019 |website=[[EDN (magazine)|EDN]]}}</ref> They are widely used in [[audio signal processing]], [[telecommunications]], [[digital image processing]], [[radar]], [[sonar]] and [[speech recognition]] systems, and in common [[consumer electronic]] devices such as [[mobile phones]], [[disk drives]] and [[high-definition television]] (HDTV) products.<ref name="computerhistory1979"/>

A '''digital signal processor''' ('''DSP''') is a specialized [[microprocessor]] chip, with its architecture optimized for the operational needs of [[digital signal processing]].<ref>{{ cite book | editor-last1 = Yovits | editor-first1 = Marshall C. | last1 = Dyer | first1 = Stephen A. | last2 = Harms | first2 = Brian K. | chapter = Digital Signal Processing | title = Advances in Computers | date = 1993-08-13 | volume = 37 | pages = 59{{hyphen}}118 | publisher = [[Academic Press]] | doi = 10.1016/S0065-2458(08)60403-9 | isbn = 978-0120121373 | issn = 0065-2458 | lccn = 59015761 | chapter-url = https://books.google.com/books?id=vL-bB7GALAwC&pg=PA104 | ol = OL10070096M | oclc = 858439915 | df = dmy-all}}</ref>{{rp|pages=104{{hyphen}}107}}<ref name="Liptak">{{ cite book | last = Liptak | first = B. G. | title = Process Control and Optimization | series = Instrument Engineers' Handbook | edition = 4th | year = 2006 | volume = 2 | pages = 11–12 | publisher = CRC Press | isbn = 978-0849310812 | url = https://books.google.com/books?id=TxKynbyaIAMC&pg=PA11 | via = [[Google Books]] }}</ref> DSPs are [[semiconductor device fabrication|fabricated]] on [[Integrated circuitMOSFET|metal–oxide–semiconductor]] (MOS) [[integrated circuit]] chips.<ref name="computerhistory1979">{{cite web |title=1979: Single Chip Digital Signal Processor Introduced |url=https://www.computerhistory.org/siliconengine/single-chip-digital-signal-processor-introduced/ |access-date=14 October 2019 |website=The Silicon Engine |publisher=[[Computer History Museum]]}}</ref><ref name="edn">{{cite web |last1=Taranovich |first1=Steve |date=August 27, 2012 |title=30 years of DSP: From a child's toy to 4G and beyond |url=https://www.edn.com/design/systems-design/4394792/30-years-of-DSP--From-a-child-s-toy-to-4G-and-beyond |access-date=14 October 2019 |website=[[EDN (magazine)|EDN]]}}</ref> They are widely used in [[audio signal processing]], [[telecommunications]], [[digital image processing]], [[radar]], [[sonar]] and [[speech recognition]] systems, and in common [[consumer electronic]] devices such as [[mobile phones]], [[disk drives]] and [[high-definition television]] (HDTV) products.<ref name="computerhistory1979"/>

The goal of a DSP is usually to measure, filter or compress continuous real-world [[analog signals]]. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such as [[mobile phone]]s because of power consumption constraints.<ref name="schaum-2004">{{cite web

| url = http://ptolemy.eecs.berkeley.edu/~kienhuis/ftp/07g.pdf

The goal of a DSP is usually to measure, filter or compress continuous real-world [[analog signals]]. Most general-purpose microprocessors can also execute digital signal processing algorithms successfully, but may not be able to keep up with such processing continuously in real-time. Also, dedicated DSPs usually have better power efficiency, thus they are more suitable in portable devices such as [[mobile phone]]s because of power consumption constraints.<ref name="schaum-2004">{{cite web

| title = Architectures and Design techniques for energy efficient embedded DSP and multimedia processing

| url = http://ptolemy.eecs.berkeley.edu/~kienhuis/ftp/07g.pdf

| date = 2005-12-24 | access-date = 2017-06-13

| title = Architectures and Design techniques for energy efficient embedded DSP and multimedia processing

| author1 = Ingrid Verbauwhede | author2 = Patrick Schaumont

| date = 2005-12-24 | access-date = 2017-06-13

| author3 = Christian Piguet | author4 = Bart Kienhuis

| author1 = Ingrid Verbauwhede | author2 = Patrick Schaumont

| publisher = rijndael.ece.vt.edu }}</ref> DSPs often use special [[memory architecture]]s that are able to fetch multiple data or instructions at the same time.

| author3 = Christian Piguet | author4 = Bart Kienhuis

| publisher = rijndael.ece.vt.edu }}</ref> DSPs often use special [[memory architecture]]s that are able to fetch multiple data or instructions at the same time.

==Overview==

[[Image:DSP block diagram.svg|thumb|410px|A typical digital processing system]]

Digital signal processing (DSP) [[algorithm]]s typically require a large number of mathematical operations to be performed quickly and repeatedly on a series of data samples. Signals (perhaps from audio or video sensors) are constantly converted from analog to digital, manipulated digitally, and then converted back to analog form. Many DSP applications have constraints on [[latency (engineering)|latency]]; that is, for the system to work, the DSP operation must be completed within some fixed time, and deferred (or batch) processing is not viable.

Most general-purpose microprocessors and operating systems can execute DSP algorithms successfully, but are not suitable for use in portable devices such as mobile phones and PDAs because of power efficiency constraints.<ref name="schaum-2004" /> A specialized DSP, however, will tend to provide a lower-cost solution, with better performance, lower latency, and no requirements for specialised cooling or large batteries.{{citation needed|date=February 2013}}

Such performance improvements have led to the introduction of digital signal processing in commercial [[communications satellite]]s where hundreds or even thousands of analog filters, switches, frequency converters and so on are required to receive and process the [[uplink]]ed signals and ready them for [[downlink]]ing, and can be replaced with specialised DSPs with significant benefits to the satellites' weight, power consumption, complexity/cost of construction, reliability and flexibility of operation. For example, the SES-12 and SES-14 satellites from operator [[SES S.A.(company)|SES]] launched in 2018, were both built by [[Airbus Defence and Space]] with 25% of capacity using DSP.<ref>''[[Beyond Frontiers]]'' Broadgate Publications (September 2016) pp22</ref>

The architecture of a DSP is optimized specifically for digital signal processing. Most also support some of the features asof an applications processor or microcontroller, since signal processing is rarely the only task of a system. Some useful features for optimizing DSP algorithms are outlined below.

==Architecture==

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===Software architecture===

By the standards of general-purpose processors, DSP instruction sets are often highly irregular; while traditional instruction sets are made up of more general instructions that allow them to perform a wider variety of operations, instruction sets optimized for digital signal processing contain instructions for common mathematical operations that occur frequently in DSP calculations. Both traditional and DSP-optimized instruction sets are able to compute any arbitrary operation but an operation that might require multiple [[ARM architecture family|ARM]] or [[x86]] instructions to compute might require only one instruction in a DSP optimized instruction set.

One implication for software architecture is that hand-optimized [[assembly language|assembly-code]] [[Subroutine|routines]] (assembly programs) are commonly packaged into libraries for re-use, instead of relying on advanced compiler technologies to handle essential algorithms. Even with modern compiler optimizations hand-optimized assembly code is more efficient and many common algorithms involved in DSP calculations are hand-written in order to take full advantage of the architectural optimizations.

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*Multiple arithmetic units may require [[memory architecture]]s to support several accesses per instruction cycle – typically supporting reading 2 data values from 2 separate data buses and the next instruction (from the instruction cache, or a 3rd program memory) simultaneously.<ref>

[http://users.ece.utexas.edu/~bevans/courses/ee382c/lectures/02_signal_processing/project1.html "Memory and DSP Processors"].

</ref><ref>{{Cite web |url=http://www.bores.com/courses/intro/chips/6_mem.htm |title="DSP processors: memory architectures" |access-date=2020-03-03 |archive-date=2020-02-17 |archive-url=https://web.archive.org/web/20200217084008/http://www.bores.com/courses/intro/chips/6_mem.htm |url-status=dead}}</ref><ref>

</ref><ref>

[http://www.bores.com/courses/intro/chips/6_mem.htm "DSP processors: memory architectures"]

</ref><ref>

[http://www.dspguide.com/ch28/3.htm "Architecture of the Digital Signal Processor"]

</ref><ref>

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</ref> and hardware loop buffers.<ref>

[https://www.analog.com/media/en/technical-documentation/technical-articles/350395352047424547665311ProgrammingTechniquesForDSPs.pdf "Understanding Advanced Processor Features Promotes Efficient Coding"].

</ref><ref>{{cite book | chapter-url=https://link.springer.com/content/pdf/10.1007/3-540-46423-9_11.pdf | doi=10.1007/3-540-46423-9_11 | chapter=Techniques for Effectively Exploiting a Zero Overhead Loop Buffer | title=Compiler Construction | series=Lecture Notes in Computer Science | date=2000 | last1=Uh | first1=Gang-Ryung | last2=Wang | first2=Yuhong | last3=Whalley | first3=David | last4=Jinturkar | first4=Sanjay | last5=Burns | first5=Chris | last6=Cao | first6=Vincent | volume=1781 | pages=157–172 | isbn=978-3-540-67263-0 }}</ref>

</ref><ref>

[https://link.springer.com/content/pdf/10.1007/3-540-46423-9_11.pdf "Techniques for Effectively Exploiting a Zero Overhead Loop Buffer"].

</ref>

====Data instructions====

*[[Saturation arithmetic]], in which operations that produce overflows will accumulate at the maximum (or minimum) values that the register can hold rather than wrapping around (maximum+1 doesn't overflow to minimum as in many general-purpose CPUs, instead it stays at maximum). Sometimes various sticky bits operation modes are available.

*[[Fixed-point arithmetic]] is often used to speed up arithmetic processing.

*Single-cycle operations to increase the benefits of [[Pipeline (computing)|pipelining]].

====Program flow====

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===Hardware architecture===

In engineering, hardware architecture refers to the identification of a system's physical components and their interrelationships. This description, often called a hardware design model, allows hardware designers to understand how their components fit into a system architecture and provides to software component designers important information needed for software development and integration. Clear definition of a hardware architecture allows the various traditional engineering disciplines (e.g., electrical and mechanical engineering) to work more effectively together to develop and manufacture new machines, devices and components.

Hardware is also an expression used within the computer engineering industry to explicitly distinguish the (electronic computer) hardware from the software that runs on it. But hardware, within the automation and software engineering disciplines, need not simply be a computer of some sort. A modern automobile runs vastly more software than the Apollo spacecraft. Also, modern aircraft cannot function without running tens of millions of computer instructions embedded and distributed throughout the aircraft and resident in both standard computer hardware and in specialized hardware components such as IC wired logic gates, analog and hybrid devices, and other digital components. The need to effectively model how separate physical components combine to form complex systems is important over a wide range of applications, including computers, personal digital assistants (PDAs), cell phones, surgical instrumentation, satellites, and submarines.

====Memory architecture====

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DSPs are usually optimized for streaming data and use special memory architectures that are able to fetch multiple data or instructions at the same time, such as the [[Harvard architecture]] or Modified [[von Neumann architecture]], which use separate program and data memories (sometimes even concurrent access on multiple data buses).

DSPs can sometimes rely on supporting code to know about cache hierarchies and the associated delays. This is a tradeoff that allows for better performance{{clarify|date=November 2015}}. In addition, extensive use of [[Direct memory access|DMA]] is employed.

=====Addressing and virtual memory=====

DSPs frequently use multi-tasking operating systems, but have no support for [[virtual memory]] or memory protection. Operating systems that use virtual memory require more time for [[context switching]] among [[process (computing)|processes]], which increases latency.

*Hardware modulo addressing

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[[File:TRW 1010J 1.jpg|thumb|TRW TDC1010 multiplier-accumulator]]

===Development===

In 1976, Richard Wiggins proposed the [[Speak & Spell (toy)|Speak & Spell]] concept to Paul Breedlove, Larry Brantingham, and Gene Frantz at [[Texas Instruments]]' Dallas research facility. Two years later in 1978, they produced the first Speak & Spell, with the technological centerpiece being the [[TMS5100]],<ref>{{cite web | publisher = IEEE | work = IEEE Milestones | title = Speak & Spell, the First Use of a Digital Signal Processing IC for Speech Generation, 1978 | url = http://www.ieeeghn.org/wiki/index.php/Milestones:Speak_%26_Spell,_the_First_Use_of_a_Digital_Signal_Processing_IC_for_Speech_Generation,_1978 | access-date = 2012-03-02 }}</ref> the industry's first digital signal processor. It also set other milestones, being the first chip to use linear predictive coding to perform [[speech synthesis]].<ref>{{cite web | author = Bogdanowicz, A. | title = IEEE Milestones Honor Three | url = http://theinstitute.ieee.org/technology-focus/technology-history/ieee-milestones-honor-four476 | work = The Institute | publisher = IEEE | date = 2009-10-06 | access-date = 2012-03-02 | archive-url = https://web.archive.org/web/20160304200210/http://theinstitute.ieee.org/technology-focus/technology-history/ieee-milestones-honor-four476 | archive-date = 2016-03-04 | url-status = dead }}</ref> The chip was made possible with a [[10 µmμm process|7{{nbsp}}µm μm]] [[PMOS logic|PMOS]] [[semiconductor device fabrication|fabrication process]].<ref>{{cite book |last1=Khan |first1=Gul N. |last2=Iniewski |first2=Krzysztof |title=Embedded and Networking Systems: Design, Software, and Implementation |date=2017 |publisher=[[CRC Press]] |isbn=9781351831567 |page=2 |url=https://books.google.com/books?id=vx8uDwAAQBAJ&pg=PR14}}</ref>

In 1978, [[American Microsystems]] (AMI) released the S2811.<ref name="computerhistory1979"/><ref name="edn"/> The AMI S2811 "signal processing peripheral", like many later DSPs, has a hardware multiplier that enables it to do [[multiply–accumulate operation]] in a single instruction.<ref>Alberto Luis Andres. [http://scholarworks.csun.edu/bitstream/handle/10211.3/126902/AndresAlberto1983.pdf "Digital Graphic Audio Equalizer"]. p. 48.</ref> The S2281 was the first [[integrated circuit]] chip specifically designed as a DSP, and fabricated using vertical metal oxide semiconductor ([[VMOS]], (V-groove MOS), a technology that had previously not been mass-produced.<ref name="edn"/> It was designed as a microprocessor peripheral, for the [[Motorola 6800]],<ref name="computerhistory1979"/> and it had to be initialized by the host. The S2811 was not successful in the market.

In 1979, [[Intel]] released the [[Intel 2920|2920]] as an "analog signal processor".<ref>{{Cite web |url=https://www.intel.com/Assets/PDF/General/35yrs.pdf#page=17 |title=Archived copy |access-date=2019-02-17 |archive-date=2020-09-29 |archive-url=https://web.archive.org/web/20200929045706/https://www.intel.com/Assets/PDF/General/35yrs.pdf#page=17 |url-status=dead }}</ref> It had an on-chip ADC/DAC with an internal signal processor, but it didn't have a hardware multiplier and was not successful in the market.

In 1980, the first stand-alone, complete DSPs – [[Nippon Electric Corporation]]'s [[NEC µPD7720μPD7720]] based on the modified Harvard architecture<ref>{{cite web |url=https://www.datasheetarchive.com/datasheet?id=03a93172fcfb5d333133fa8d7fb1d6fa7cf492&type=M&term=upd7720 |title=NEC Electronics Inc. μPD77C20A, 7720A, 77P20 Digital Signal Processors |page=1 |accessdate=2023-11-13}}</ref> and [[AT&T Corporation|AT&T]]'s [[AT&T DSP1|DSP1]] – were presented at the [[International Solid-State Circuits Conference]] '80. Both processors were inspired by the research in [[public switched telephone network]] (PSTN) [[telecommunicationtelecommunications]]s. The µPD7720μPD7720, introduced for [[voiceband]] applications, was one of the most commercially successful early DSPs.<ref name="computerhistory1979"/>

The Altamira DX-1 was another early DSP, utilizing quad integer pipelines with delayed branches and branch prediction.{{citation needed|reason=no mention on the web, except of WP text copies and translations|date=December 2014}}

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==Modern DSPs==

Modern signal processors yield greater performance; this is due in part to both technological and architectural advancements like lower design rules, fast-access two-level cache, (E)[[Direct memory access|DMA]] circuitry, and a wider bus system. Not all DSPs provide the same speed and many kinds of signal processors exist, each one of them being better suited for a specific task, ranging in price from about US$1.50 to US$300.

[[Texas Instruments]] produces the [[TMS320C6000|C6000]] series DSPs, which have clock speeds of 1.2&nbsp;GHz and implement separate instruction and data caches. They also have an 8 &nbsp;MiB 2nd level cache and 64 EDMA channels. The top models are capable of as many as 8000 MIPS ([[millions of instructions per second]]), use VLIW ([[very long instruction word]]), perform eight operations per clock-cycle and are compatible with a broad range of external peripherals and various buses (PCI/serial/etc). TMS320C6474 chips each have three such DSPs, and the newest generation C6000 chips support floating point as well as fixed point processing.

[[Freescale]] produces a multi-core DSP family, the MSC81xx. The MSC81xx is based on StarCore Architecture processors and the latest MSC8144 DSP combines four programmable SC3400 StarCore DSP cores. Each SC3400 StarCore DSP core has a clock speed of 1&nbsp;GHz.

[[XMOS]] produces a multi-core multi-threaded line of processor well suited to DSP operations, They come in various speeds ranging from 400 to 1600 MIPS. The processors have a multi-threaded architecture that allows up to 8 real-time threads per core, meaning that a 4 core device would support up to 32 real time threads. Threads communicate between each other with buffered channels that are capable of up to 80 &nbsp;Mbit/s. The devices are easily programmable in C and aim at bridging the gap between conventional micro-controllers and FPGAs

[[CEVA, Inc.]] produces and licenses three distinct families of DSPs. Perhaps the best known and most widely deployed is the CEVA-TeakLite DSP family, a classic memory-based architecture, with 16-bit or 32-bit word-widths and single or dual [[Multiply–accumulate operation|MACs]]. The CEVA-X DSP family offers a combination of VLIW and SIMD architectures, with different members of the family offering dual or quad 16-bit MACs. The CEVA-XC DSP family targets [[Software-defined radio|Software-defined Radio (SDR)]] modem designs and leverages a unique combination of VLIW and Vector architectures with 32 16-bit MACs.

[[Analog Devices]] produce the [[Super Harvard Architecture Single-Chip Computer|SHARC]]-based DSP and range in performance from 66&nbsp;MHz/198 [[MFLOPS]] (million floating-point operations per second) to 400&nbsp;MHz/2400 MFLOPS. Some models support multiple [[binary multiplier|multiplier]]s and [[Arithmetic logic unit|ALU]]s, [[Single instruction, multiple data|SIMD]] instructions and audio processing-specific components and peripherals. The [[Blackfin]] family of embedded digital signal processors combine the features of a DSP with those of a general use processor. As a result, these processors can run simple [[operating system]]s like [[μCLinux]], velocity and [[Nucleus RTOS]] while operating on real-time data. The SHARC-based ADSP-210xx provides both [[delay slot|delayed branches]] and non-delayed branches.<ref>{{cite web |url=https://www.brown.edu/Departments/Engineering/Courses/En164/files/lab3_files/sharc_application_manual/chap1.pdf |title=Introduction of ADSP-21000 Family digital signal processors. |page=6 |accessdate=2023-12-01}}</ref>

[[NXP Semiconductors]] produce DSPs based on [[TriMedia (mediaprocessor)|TriMedia]] [[VLIW]] technology, optimized for audio and video processing. In some products the DSP core is hidden as a fixed-function block into a [[System-on-a-chip|SoC]], but NXP also provides a range of flexible single core media processors. The TriMedia media processors support both [[fixed-point arithmetic]] as well as [[floating-point arithmetic]], and have specific instructions to deal with complex filters and entropy coding.

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* [[MDSP]] – a multiprocessor DSP

* [[OpenCL]]

* [[Sound card]]

==References==

{{Reflist|30em|refs=

<!--<ref name="Stankovic_2012">{{cite journal | last1 = Stanković | first1 = Radomir S. | last2 = Astola | first2 = Jaakko T. |title = Reminiscences of the Early Work in DCT: Interview with K.R. Rao | journal = Reprints from the Early Days of Information Sciences | publisher = Tampere International Center for Signal Processing | date = 2012 | volume = 60 | url = https://ethw.org/w/images/1/19/Report-60.pdf | access-date = 2021-12-30 | archive-url = https://web.archive.org/web/20211230214050/https://ethw.org/w/images/1/19/Report-60.pdf | archive-date = 2021-12-30 | url-status = live | issn = 1456-2774 | isbn = 978-9521528187 | via = [[Engineering and Technology History Wiki|ETHW]] | df = dmy-all}}</ref>-->

}}

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*[http://www.dspguide.com DSP Online Book]

*[http://www.bdti.com/pocket/pocket.htm Pocket Guide to Processors for DSP - Berkeley Design Technology, INC]

{{CPUProcessor technologies}}

{{Authority control}}

{{Hardware acceleration}}

{{Authority control}}

[[Category:Digital signal processing]]