Programmable interrupt controller: Difference between revisions

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{{Short description|Integrated circuit that handles interrupts}}

{{distinguish| PIC microcontroller }}

{{Multiple issues|

{{one source|date=February 2014}}

{{nomore footnotes|date=September 2013}}

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In [[computing]], a '''programmable interrupt controller''' ('''PIC''') is an [[integrated circuit]] that helps a [[microprocessor]] (or [[CPU]]) handle [[Interrupt request (PC architecture)|interrupt requests]] (IRQs) coming from multiple different sources (like external I/O devices) which may occur simultaneously.<ref>{{cite journal|title=A Revisitation of Kernel Synchronization Schemes

|author1=Christopher Small |author2=Stephen Manley

In [[computing]], a '''programmable interrupt controller''' ('''PIC''') is a device that is used to combine several sources of [[interrupt]] onto one or more [[CPU]] lines, while allowing priority levels to be assigned to its interrupt outputs. When the device has multiple interrupt outputs to assert, it asserts them in the order of their relative priority. Common modes of a PIC include hard priorities, rotating priorities, and cascading priorities.{{Citation needed|date=July 2011}} PICs often allow the cascading of their outputs to inputs between each other.

|url=https://static.usenix.org/publications/library/proceedings/ana97/full_papers/small/small.html}}</ref> It helps prioritize IRQs so that the CPU switches execution to the most appropriate [[interrupt handler]] (ISR) after the PIC assesses the IRQs' relative priorities. Common modes of interrupt priority include hard priorities, rotating priorities, and cascading priorities.{{Citation needed|date=July 2011}} PICs often allow mapping input to outputs in a configurable way. On the [[PC architecture]] PIC are typically embedded into a [[Southbridge (computing)|southbridge chip]] whose internal architecture is defined by the chipset vendor's standards.

==Common features==

PICs typically have a common set of registers: Interruptinterrupt Requestrequest Registerregister (IRR), Inin-Serviceservice Registerregister (ISR), Interruptand Maskinterrupt Registermask register (IMR). The IRR specifies which interrupts are pending acknowledgement, and is typically a symbolic register which can not be directly accessed. The ISR register specifies which interrupts have been acknowledged, but are still waiting for an [[Endend of interrupt|End Of Interrupt]] (EOI). The IMR specifies which interrupts are to be ignored and not acknowledged. A simple register schema such as this allows up to two distinct interrupt requests to be outstanding at one time, one waiting for acknowledgement, and one waiting for EOI.

There are a number of common priority schemas in PICs including hard priorities, specific priorities, and rotating priorities.

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==Well-known types==

One of the best known PICs, the [[Intel 8259|8259A]], was included in the [[x86 architecture|x86]] PC. In modern times, this is not included as a separate chip in an x86 PC, but rather as part of the motherboard's [[Southbridge (computing)|southbridge]] chipset.<ref>{{Cite web| title=82371AB PCI-TO-ISA / IDE Xcelerator (PIIX4) | url=https://www.intel.com/Assets/PDF/datasheet/290562.pdf | archive-url=https://web.archive.org/web/20090203012354/http://www.intel.com:80/Assets/PDF/datasheet/290562.pdf | archive-date=2009-02-03}}</ref> In other cases, it has been replaced by the newer [[Advanced Programmable Interrupt Controller]]s which support more interrupt outputs and more flexible priority schemas.

<br />

==See also==

* [[Intel 8259]] – notable PIC from Intel

* [[Advanced Programmable Interrupt Controller]] (APIC)

* [[OpenPIC and IBM MPIC]]

* [[Inter-processor interrupt]] (IPI)

* [[Interrupt]]

* [[Interrupt handler]]

* [[Interrupt request]] (IRQ)

* [[Interrupt latency]]

* [[Non-maskable interrupt]] (NMI)

* [[IRQL (Windows)]]

*

==Further reading==

More information on the Intel APIC can be found in the ''IA-32 Intel Architecture Software Developer's Manual, Volume 3A: System Programming Guide, Part 1, Chapter 10'', freely available on the [[Intel]] website.

* {{Cite web |date=2023-06-22 |title=Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A |url=https://www.intel.com/content/www/us/en/content-details/782158/intel-64-and-ia-32-architectures-software-developer-s-manual-combined-volumes-1-2a-2b-2c-2d-3a-3b-3c-3d-and-4.html?wapkw=intel%2064%20and%20ia-32%20architectures%20software%20developer%27s%20manual&docid=782161 |access-date=2025-03-28 |website=[[Intel]]}}

==References==

{{Reflist}}

==External links==

* [https://web.archive.org/web/20180408090800/http://www.fullchipdesign.com/tyh/interrupt_controller_vic.htm Interrupt controller and associated registers.]

* [http://www.intel.com/Assets/PDF/manual/253668.pdf IA-32 Intel Architecture Software Developer's Manual, Volume 3A]

* [http://www.fullchipdesign.com/tyh/interrupt_controller_vic.htm Interrupt controller and associated registers.]

[[Category:Motherboard]]