Logic optimization: Difference between revisions

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{{short description|Process in  digital electronics  and  integrated circuit design}}

{{other uses|Minimisation (disambiguation){{!}}Minimisation}}

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{{Use dmy dates|date=May 2019|cs1-dates=y}}

{{Use list-defined references|date=January 2022}}

{{Use dmy dates|date=May 2019|cs1-dates=y}}

'''Logic optimization''' is a process of finding an equivalent representation of the specified [[logic circuit]] under one or more specified constraints. This process is a part of a [[logic synthesis]] applied in [[digital electronics]] and [[integrated circuit design]].

Generally, the circuit is constrained to a minimum chip area meeting a predefined response delay. The goal of logic optimization of a given circuit is to obtain the smallest [[logic circuit]] that evaluates to the same values as the original one.<ref name="Maxfield_2008"/> TheUsually, the smaller circuit with the same function is cheaper,<ref name="Balasanyan-Aghagulyan-Wuttke-Henke_2018"/> takes less space, [[Power efficiency|consumes less power]], havehas shorter latency, and minimizes risks of unexpected [[Crosstalk|cross-talk]], [[Hazard (logic)|hazard of delayed signal processing]], and other issues present at the nano-scale level of metallic structures on aan [[integrated circuit]].

In terms of [[Boolean algebra]], the optimization of a complex [[booleanBoolean expression]] is a process of finding a simpler one, which would upon evaluation ultimately produce the same results as the original one.

==Motivation==

The problem with having a complicated [[Electronic circuit|circuit]] (i.e. one with many elements, such as [[logic gate]]s) is that each element takes up physical space in its implementation and costs time and money to produce in itself. Circuit minimization may be one form of logic optimization used to reduce the area of complex logic in [[integrated circuit]]s.

With the advent of [[logic synthesis]], one of the biggest challenges faced by the [[electronic design automation]] (EDA) industry was to find the most simple circuit representation of the given design description.<ref group="nb" name="NB_Netlist"/> While [[two-level logic optimization]] had long existed in the form of the [[Quine–McCluskey algorithm]], later followed by the [[Espresso heuristic logic minimizer]], the rapidly improving chip densities, and the wide adoption of [[Hardware description language]]s for circuit description, formalized the logic optimization ___domain as it exists today, including [[Logic Friday]] (graphical interface), Minilog, and ESPRESSO-IISOJS (many-valued logic).<ref>{{Cite journal |last=Theobald |first=M. |last2=Nowick |first2=S. M. |date=November 1998 |title=Fast heuristic and exact algorithms for two-level hazard-free logic minimization |url=https://academiccommons.columbia.edu/doi/10.7916/D8N58V58/download |journal=IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |volume=17 |issue=11 |pages=1130–1147 |doi=10.1109/43.736186}}</ref>

== Methods ==

The methods of logic circuit simplifications are equally applicable to the [[#Boolean expression minimization|booleanBoolean expression minimization]].

=== Classification ===

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Graphical minimization methods for two-level logic include:

* ''[[Euler diagram]]'' (aka ''Eulerian circle'') (1768) by [[Leonhard P. Euler]] (1707–1783)

* ''[[Venn diagram]]'' (1880) by [[John Venn]] (1834–1923)<ref name="Venn_1880_1" /><ref name="Venn_1880_2" />

* ''[[Karnaugh map]]'' (1953) by [[Maurice Karnaugh]] (1924–)<ref name="Karnaugh_1953" /><ref name="Curtis_1962" />

and many others have been developed.

=== {{Anchor|Circuit minimization in Boolean algebra}}Boolean expression minimization ===

{{Clean upCleanup|date=October 2021|reason=We need more consistent, simpler and prose-like summary on every method|section}}

The same methods of booleanBoolean expression minimization (simplification) listed below may be applied to the circuit optimization.

For the case when the Boolean function is specified by a circuit (that is, we want to find an equivalent circuit of minimum size possible), the unbounded circuit minimization problem was long-conjectured to be [[polynomial hierarchy|<math>\Sigma_2^P</math>-complete]] in [[time complexity]] (the complexity class of decision problems that can be solved on a deterministic Turing machine in polynomial time), a result finally proved in 2008,<ref name="Buchfuhrer_2011"/> but there are effective heuristics such as [[Karnaugh map]]s and the [[Quine–McCluskey algorithm]] that facilitate the process.

Boolean function minimizing methods include:

* [[Archie Blake (mathematician)|Blake]]–[[Platon Poretsky|Poretsky]] method

* [[Nelson method]]<ref name="Nelson_1955_1"/><ref name="Nelson_1955_2"/><ref name="Lipp_2011"/><ref name="Riznyk_2017"/><ref name="Riznyk_2018"/>

* [[Quine–McCluskey algorithm]]

* Method of algebraic transformations

* [[Petrick's method]]

* Roth method<ref name="Roth_1957"/><ref name="Roth_1958"/><ref name="Roth_1960"/>

* Kudielka method<ref name="Kudielka_1960"/><ref name="Kudielka_1961"/><ref name="Kudielka_1962"/>

* Wells method<ref name="Wells_1962"/>

* {{anchor|Scheinman}}Scheinman's binary method<ref name="Scheinman_1962"/><ref name="Föllinger-Weber_1967"/>

* a method of minimizing functions in bases YES-NO and OR-NOT (Schaeffer and Pierce basis)

* method of undetermined coefficients

* hypercube method

* functional decomposition method

=== EspressoOptimal heuristicmulti-level logic minimizermethods ===

Methods that find optimal circuit representations of Boolean functions are often referred to as ''exact synthesis'' in the literature. Due to the computational complexity, exact synthesis is tractable only for small Boolean functions. Recent approaches map the optimization problem to a [[Satisfiability|Boolean satisfiability]] problem.<ref>{{cite web |last1=Haaswijk |first1=Winston |title=SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism |url=https://si2.epfl.ch/~demichel/publications/archive/2020/winston-exact.pdf |website=EPFL |access-date=7 December 2022}}</ref><ref>{{cite web |last1=Haaswijk |first1=Winston |title=SAT-Based Exact Synthesis for Multi-Level Logic Networks |url=https://si2.epfl.ch/~demichel/graduates/theses/winston.pdf |website=EPFL |access-date=7 December 2022}}</ref> This allows finding optimal circuit representations using a [[SAT solver]].

{{Excerpt|Espresso heuristic logic minimizer|ESPRESSO algorithm}}

=== Heuristic methods ===

A [[heuristic]] method uses established rules that solve a practical useful subset of the much larger possible set of problems. The heuristic method may not produce the theoretically optimum solution, but if useful, will provide most of the optimization desired with a minimum of effort. An example of a computer system that uses heuristic methods for logic optimization is the [[Espresso heuristic logic minimizer]].

===Two-level versus multi-level representations===

While a two-level circuit representation of circuits strictly refers to the flattened view of the circuit in terms of SOPs ([[sum-of-products]]) &mdash; which is more applicable to a [[Programmable logic array|PLA]] implementation of the design{{Clarify|date=February 2010}} &mdash; a [[multi-level representation]] is a more generic view of the circuit in terms of arbitrarily connected SOPs, POSs ([[product-of-sums]]), factored form etc. Logic optimization algorithms generally work either on the structural (SOPs, factored form) or functional representation ([[Binarybinary decision diagramsdiagram]]s, Algebraic[[algebraic Decisiondecision Diagrams (ADDs)diagram]]s) representation of the circuit. In sum-of-products (SOP) form, AND gates form the smallest unit and are stitched together using ORs, whereas in product-of-sums (POS) form it is opposite. POS form requires parentheses to group the OR terms together under AND gates, because OR has lower precedence than AND. Both SOP and POS forms translate nicely into circuit logic.

If we have two functions ''F''₁ and ''F''₂:

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While the number of levels here is 3, the total number of product terms and literals reduce {{Quantify|date=February 2010}} because of the sharing of the term B + C.

Similarly, we distinguish between [[SequentialCombinational logic|sequentialcombinational circuits]] and [[CombinationalSequential logic|combinationalsequential circuits]],. Combinational circuits produce their outputs based only on the current whoseinputs. behaviorThey can be describedrepresented inby terms ofBoolean [[finite-stateRelation machine(mathematics)|relations]]. stateSome tables/diagramsexamples orare by[[priority Booleanencoder]]s, functions[[binary anddecoder]]s, relations[[multiplexer]]s, respectively[[demultiplexer]]s.

Combinational circuits are defined as the time independent circuits which do not depends upon previous inputs to generate any output are termed as combinational circuits. Examples – [[Encoder]], [[Decoder]], [[Multiplexer]], [[Demultiplexer]].

Sequential circuits areproduce thosetheir whichoutput are dependentbased on clockboth cyclescurrent and dependspast inputs, depending on presenta asclock wellsignal asto pastdistinguish the previous inputs tofrom generatethe anycurrent outputinputs. ExamplesThey –can be represented by finite state machines. Some examples are [[Flip-flop (electronics)|flip-flops]], and [[CountersCounter (digital)|counters]].

==Example==

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* [[Function decomposition]]

* [[Gate underutilization]]

* [[Logic redundancy]]

* <!-- some of the Wikiversity/Wikibook contents could be used to create a local article at -->[[Harvard minimizing chart]] [[:wikiversity:Harvard chart method|(Wikiversity)]] [[:wikibooks:Harvard Chart Method|(Wikibooks)]]

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== References ==

{{reflist|refs=

<ref name="Maxfield_2008">{{cite book |title=FPGAs |chapter=Chapter 5: "Traditional" Design Flows |author-last=Maxfield |author-first=Clive "Max" |date=2008-01-01 |editor-last=Maxfield |editor-first=Clive "Max" |series=Instant Access |publication-place=Burlington |publisher=[[Newnes (publisher)|Newnes]] / [[Elsevier Inc.]] |isbn=978-0-7506-8974-8 |<!-- chapter- -->doi=10.1016/B978-0-7506-8974-8.00005-3 |pages=75–106 |chapter-url=https://www.sciencedirect.com/science/article/pii/B9780750689748000053 |access-date=2021-10-04 |url-status=live |archive-url= |archive-date=}}</ref>

<ref name="Balasanyan-Aghagulyan-Wuttke-Henke_2018">{{cite web |title=Digital Electronics |author-last1=Balasanyan |author-first1=Seyran |author-last2=Aghagulyan |author-first2=Mane |author-last3=Wuttke |author-first3=Heinz-Dietrich |author-last4=Henke |author-first4=Karsten |date=2018-05-16 |id=DesIRE |series=Bachelor Embedded Systems - Year Group |publisher=Tempus |pages= |url=https://ec.europa.eu/programmes/erasmus-plus/project-result-content/120e4810-0d29-4397-9ad4-b4091c2e3d19/Digital%20Electronics.pdf |access-date=2021-10-04 |url-status=live |archive-url=https://web.archive.org/web/20211004200546/https://ec.europa.eu/programmes/erasmus-plus/project-result-content/120e4810-0d29-4397-9ad4-b4091c2e3d19/Digital%20Electronics.pdf |archive-date=2021-10-04}} (101 pages)</ref>

<ref name="Buchfuhrer_2011">{{cite journal |doi=10.1016/j.jcss.2010.06.011 |title=The complexity of Boolean formula minimization |journal=[[Journal of Computer and System Sciences]] |volume=77 |issue=1 |pages=142–153 |date=January 2011 |___location=Computer Science Department, [[California Institute of Technology]], Pasadena, California, USA |author-last1=Buchfuhrer |author-first1=David |author-last2=Umans |author-first2=Christopher |author-link2=Christopher Umans |publisher=[[Elsevier Inc.]] |url=http://users.cms.caltech.edu/~umans/papers/BU07.pdf}} This is an extended version of the conference paper: {{cite book |doi=10.1007/978-3-540-70575-8_3 |chapter=The Complexity of Boolean Formula Minimization |title=Proceedings of Automata, Languages and Programming, 35th International Colloquium (ICALP) |volume=5125 |pages=24–35 |publisher=[[Springer-Verlag]] |publication-place=Berlin / Heidelberg, Germany |series=[[Lecture Notes in Computer Science]] |date=2008 |author-last1=Buchfuhrer |author-first1=David |author-last2=Umans |author-first2=Christopher |author-link2=Christopher Umans |isbn=978-3-540-70574-1 |url=http://users.cms.caltech.edu/~umans/papers/BU07.pdf |access-date=2018-01-14 |url-status=live |archive-url=https://web.archive.org/web/20180114141842/http://users.cms.caltech.edu/~umans/papers/BU07.pdf |archive-date=2018-01-14}}</ref>

<ref name="Venn_1880_1">{{cite journal |author-last=Venn |author-first=John |author-link=John Venn |title=I. On the Diagrammatic and Mechanical Representation of Propositions and Reasonings |journal=[[The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science]] |volume=10 |issue=59 |date=July 1880 |series=5 |doi=10.1080/14786448008626877 |pages=1–18 |url=https://www.cis.upenn.edu/~bhusnur4/cit592_fall2014/venn%20diagrams.pdf |url-status=live |archive-url=https://web.archive.org/web/20170516204620/https://www.cis.upenn.edu/~bhusnur4/cit592_fall2014/venn%20diagrams.pdf |archive-date=2017-05-16}} [http://www.tandfonline.com/doi/abs/10.1080/14786448008626877] [https://books.google.com/books?id=k68vAQAAIAAJ&pg=PA1]</ref>

<ref name="Venn_1880_2">{{cite journal |author-last=Venn |author-first=John |author-link=John Venn |date=1880 |url=https://archive.org/stream/proceedingsofcam4188083camb#page/47/mode/1up |title=On the employment of geometrical diagrams for the sensible representations of logical propositions |journal=[[Proceedings of the Cambridge Philosophical Society]] |volume=4 |pages=47–59}}</ref>

<ref name="Buchfuhrer_2011">{{cite journal |doi=10.1016/j.jcss.2010.06.011 |title=The complexity of Boolean formula minimization |journal=[[Journal of Computer and System Sciences]] (JCSS) |volume=77 |issue=1 |pages=142–153 |date=January 2011 |___location=Computer Science Department, [[California Institute of Technology]], Pasadena, California, USA |author-last1=Buchfuhrer |author-first1=David |author-last2=Umans |author-first2=Christopher |author-link2=Christopher Umans |publisher=[[Elsevier Inc.]] |url=http://users.cms.caltech.edu/~umans/papers/BU07.pdf}} This is an extended version of the conference paper: {{cite book |doi=10.1007/978-3-540-70575-8_3 |chapter=The Complexity of Boolean Formula Minimization |title=Proceedings of Automata, Languages and Programming |work=35th International Colloquium (ICALP) |volume=5125 |pages=24–35 |publisher=[[Springer-Verlag]] |publication-place=Berlin / Heidelberg, Germany |series=[[Lecture Notes in Computer Science]] (LNCS) |date=2008 |author-last1=Buchfuhrer |author-first1=David |author-last2=Umans |author-first2=Christopher |author-link2=Christopher Umans |isbn=978-3-540-70574-1 |url=http://users.cms.caltech.edu/~umans/papers/BU07.pdf |access-date=2018-01-14 |url-status=live |archive-url=https://web.archive.org/web/20180114141842/http://users.cms.caltech.edu/~umans/papers/BU07.pdf |archive-date=2018-01-14}}</ref>

<ref name="Mano_2014">{{cite book |author-first1=M. Morris |author-last1=Mano |author-first2=Charles R. |author-last2=Kime |title=Logic and Computer Design Fundamentals |edition=4th new international |publisher=[[Pearson Education Limited]] |date=2014 |page=54 |isbn=978-1-292-02468-4}}</ref>

<ref name="Aiken_1952">{{cite book |title=Synthesis of electronic computing and control circuits |orig-date=January 1951 |date=1952 |edition=second printing, revised |chapter=Chapter V: Minimizing charts |pages=preface, 50–67 |author-first1=Howard Hathaway |author-last1=Aiken |author-link1=Howard Hathaway Aiken |author-first2=Gerrit Anne |author-last2=Blaauw |author-link2=Gerrit Anne Blaauw |author-first3=William |author-last3=Burkhart |author-first4=Robert J. |author-last4=Burns |author-first5=Lloyd |author-last5=Cali |author-first6=Michele |author-last6=Canepa |author-first7=Carmela M. |author-last7=Ciampa |author-first8=Charles A. |author-last8=Coolidge, Jr. |author-first9=Joseph R. |author-last9=Fucarile |author-first10=J. Orten |author-last10=Gadd, Jr. |author-first11=Frank F. |author-last11=Gucker |author-first12=John A. |author-last12=Harr |author-first13=Robert L. |author-last13=Hawkins |author-first14=Miles V. |author-last14=Hayes |author-first15=Richard |author-last15=Hofheimer |author-first16=William F. |author-last16=Hulme |author-first17=Betty L. |author-last17=Jennings |author-first18=Stanley A. |author-last18=Johnson |author-first19=Theodore |author-last19=Kalin |author-first20=Marshall |author-last20=Kincaid |author-first21=E. Edward |author-last21=Lucchini |author-first22=William |author-last22=Minty |author-first23=Benjamin L. |author-last23=Moore |author-first24=Joseph |author-last24=Remmes |author-first25=Robert J. |author-last25=Rinn |author-first26=John W. |author-last26=Roche |author-first27=Jacquelin |author-last27=Sanbord |author-first28=Warren L. |author-last28=Semon |author-first29=Theodore |author-last29=Singer |author-first30=Dexter |author-last30=Smith |author-first31=Leonard |author-last31=Smith |author-first32=Peter F. |author-last32=Strong |author-first33=Helene V. |author-last33=Thomas |author-first34=An |author-last34=Wang |author-link34=An Wang |author-first35=Martha L. |author-last35=Whitehouse |author-first36=Holly B. |author-last36=Wilkins |author-first37=Robert E. |author-last37=Wilkins |author-first38=Way Dong |author-last38=Woo |author-first39=Elbert P. |author-last39=Little |author-first40=M. Scudder |author-last40=McDowell |___location=Write-Patterson Air Force Base |publisher=[[Harvard University Press]] (Cambridge, Massachusetts, USA) / Geoffrey Cumberlege Oxford University Press (London) |volume=XXVII |series=The Annals of the Computation Laboratory of Harvard University |id=ark:/13960/t4zh1t09d <!-- |ia: in.ernet.dli.2015.509288 --> |url=https://archive.org/stream/in.ernet.dli.2015.509288/2015.509288.Synthesis-Of |access-date=2017-04-16 |quote-page=preface |quote=[…] Martha Whitehouse constructed the minimizing charts used so profusely throughout this book, and in addition prepared minimizing charts of seven and eight variables for experimental purposes. […] Hence, the present writer is obliged to record that the general algebraic approach, the switching function, the vacuum-tube operator, and the minimizing chart are his proposals, and that he is responsible for their inclusion herein. […]}} (2+x+278+2 pages) (NB. Work commenced in April 1948.)</ref>

<ref name="Ashenhurst_1952">{{cite journal |title=The decomposition of switching functions |author-first=Robert "Bob" Lovett |author-last=Ashenhurst<!-- 1929-08-09 – 2009-10-21 https://web.archive.org/web/20210331183941/https://cacm.acm.org/magazines/2010/1/55753-robert-lovett-ashenhurst-1929-2009/fulltext --> |author-link=:d:Q102124175 |journal=Bell Laboratories' Report |publisher=[[Bell Laboratories]] |___location=[[Harvard Computation Laboratory]], Harvard University, Cambridge, Massachusetts, USA |type=report |number=<!-- HU -->BL-1 |id=PB122812 <!-- |at=Sec. II -->|pages=II-1–II-37 |date=January 1953 |orig-date=1952-09-01, 1953-01-01}} (37 of 98 pages) (NB. This article was reprinted in the appendix of {{citeref|Curtis|1962|Curtis (1962)|style=plain}}, pp. 571–602<!-- some sources incorrectly give –603 -->.); another article of the same title was published as: {{cite journal |title=The decomposition of switching functions |author-first=Robert "Bob" Lovett |author-last=Ashenhurst |author-link=:d:Q102124175 |journal=Bell Laboratories' Report&nbsp;/ Theory of Switching |editor-first1=Howard Hathaway |editor-last1=Aiken |editor-link1=Howard Hathaway Aiken |publisher=[[Bell Laboratories]] |___location=[[Harvard Computation Laboratory]], Harvard University, Cambridge, Massachusetts, USA |type=report |number=<!-- HU -->BL-16 |id=PB147348 <!-- |at=Sec. III --> |pages=III-1–III-72 |date=December 1956 |orig-date=1956-05-01, 1956-12-01}} (72 of 193 pages); an updated article was later published under the same title as: {{cite journal |title=The Decomposition of Switching Functions |author-first=Robert "Bob" Lovett |author-last=Ashenhurst |author-link=:d:Q102124175 |journal=Proceedings of the International Symposium on the Theory of Switching, Part I |volume=XXIX |series=The Annals of the Computation Laboratory of Harvard University |publisher=[[Harvard University Press]] |publication-place=Harvard University, Cambridge, Massachusetts, USA |publication-date=1959<!-- April? --> |date=1957-04-02<!-- /05 --> |pages=74–116 |url=https://people.eecs.berkeley.edu/~alanmi/publications/other/ashenhurst1959.pdf |access-date=2021-03-29 |url-status=live |archive-url=https://web.archive.org/web/20210328112418/https://people.eecs.berkeley.edu/~alanmi/publications/other/ashenhurst1959.pdf |archive-date=2021-03-28}} (43 pages)</ref>

<ref name="Singer_1953">{{cite journal |title=The Decomposition Chart as a Theoretical Aid |author-first=Theodore "Ted" |author-last=Singer<!-- 1916-04-30 – 1991-02-06 https://web.archive.org/web/20210331184116/https://www.ancientfaces.com/person/theodore-singer-birth-1916-death-1991/6279100 --> |___location=[[Harvard Computation Laboratory]], Harvard University, Cambridge, Massachusetts, USA |publisher=[[Bell Laboratories]] |type=report |journal=Bell Laboratories' Report |number=<!-- HU -->BL-4 |id=PB122815 |date=July 1953 |orig-date=1953-04-01, 1953-07-01 <!-- |at=Sec. III --> |pages=III-1–III-28}} (28 of 149 pages) (NB. This article was reprinted in the appendix of {{citeref|Curtis|1962|Curtis (1962)|style=plain}}, pp. 602–620.)</ref>

<ref name="Ashenhurst_1953">{{cite journal |title=Non-disjoint Decomposition |author-first=Robert "Bob" Lovett |author-last=Ashenhurst |author-link=:d:Q102124175 |journal=Bell Laboratories' Report |publisher=[[Bell Laboratories]] |___location=[[Harvard Computation Laboratory]], Harvard University, Cambridge, Massachusetts, USA |type=report |number=<!-- HU -->BL-4 |id=PB122815 <!-- |at=Sec. IV --> |date=July 1953 |orig-date=1953-04-01, 1953-07-01 |pages=IV-1–IV-12}} (12 of 149 pages) (NB. This article was reprinted in the appendix of {{citeref|Curtis|1962|Curtis (1962)|style=plain}}, pp. 620–630.)</ref>

<ref name="Phister_1959">{{cite book |title=Logical design of digital computers |author-first=Montgomery |author-last=Phister, Jr. |publisher=[[John Wiley & Sons Inc.]] |date=April 1959 |orig-date=December 1958 |edition=3rd printing, 1st |series=Digital Design and Applications |___location=New York, USA |isbn=0-47168805-3 |id={{ISBN|978-0-47168805-1}} |lccn=58-6082 |mr=0093930 |pages=75–83}} (xvi+408 pages)</ref>

<ref name="Curtis_1962">{{cite book |title=A new approach to the design of switching circuits |author-first=Herbert Allen |author-last=Curtis |publisher=[[D. van Nostrand Company, Inc.]] |date=1962 |___location=Princeton, New Jersey, USA |edition=1 |series=The Bell Laboratories Series |s2cid=57068910 |oclc=1036797958 |isbn=0-44201794-4 |id={{ISBN|978-0-44201794-1}}. ark:/13960/t56d6st0q <!-- |ia=newapproachtodes00curt -->}} (viii+635 pages) (NB. This book was reprinted by Chin Jih in 1969.)</ref>

<ref name="Karnaugh_1953">{{cite journal |author-last=Karnaugh |author-first=Maurice |author-link=Maurice Karnaugh |title=The Map Method for Synthesis of Combinational Logic Circuits |journal=[[Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics]] |volume=72 |issue=5 |pages=593–599 |date=November 1953 |orig-date=1953-04-23, 1953-03-17 |id=Paper 53-217 |doi=10.1109/TCE.1953.6371932 |url=http://philectrosophy.com/documents/The%20Map%20Method%20For%20Synthesis%20of.pdf |access-date=2017-04-16 |url-status=dead |archive-url=https://web.archive.org/web/20170416232229/http://philectrosophy.com/documents/The%20Map%20Method%20For%20Synthesis%20of.pdf |archive-date=2017-04-16}}</ref>

<ref name="Roth_1957">{{cite journal |title=Algebraic topological methods in synthesis |author-last=Roth |author-first=John Paul |journal=Proceedings of an International Symposium on the Theory of Switching, Part I |publication-date=July 1959 |orig-date=April 1957-04-02/05 |series=The Annals of the Harvard Computation Laboratory |volume=XXIX<!-- recheck --> |publisher=[[Harvard University Press]] |___location=Cambridge, Massachusetts, USA |pages=57–73}}</ref>

<ref name="Roth_1958">{{cite journal |title=Algebraic Topological Methods for the Synthesis of Switching Systems, Part I |author-last=Roth |author-first=John Paul |journal=Transactions of the American Mathematical Society |volume=88 |number=2 |date=July 1958 |doi=10.2307/1993216 |doi-access=free |jstor=1993216 |pages=301–326}} (26 pages)</ref>

<ref name="Roth_1960">{{cite journal |title=Minimization over Boolean Trees |author-last=Roth |author-first=John Paul<!-- "J. Paul Roth" (1923-2005), member of the IBM T.J. Watson Research Center for many years; head of the Switching Research group in 1957. --> |journal=[[IBM Journal of Research and Development]] |volume=4 |number=5 |date=November 1960 |doi=10.1147/rd.45.0543 |issn=0018-8646 |eissn=0018-8646 |pages=543–558}}</ref>

<ref name="Kudielka_1960">{{cite book |title=Programs for Logical Data Processing |chapter=4–5 |author-first1=Viktor |author-last1=Kudielka |author-first2=Kurt |author-last2=Walk |author-first3=Kurt |author-last3=Bandat |author-first4=Peter |author-last4=Lucas |author-link4=Peter Lucas (computer scientist) |author-first5=Heinrich "Heinz" Josef |author-last5=Zemanek |author-link5=Heinrich Josef Zemanek |editor-first=Heinrich "Heinz" Josef |editor-last=Zemanek |editor-link=Heinrich Josef Zemanek |id=European Research Office Contract DA-91-591-EC-1062 |work=[[Mailüfterl]] |type=Final report |publisher=[[Technical University of Vienna]], Institut für Nachrichtentechnik |___location=Vienna, Austria |date=1960-02-29 |url=https://www.researchgate.net/publication/294894251_Programs_for_Logical_Data_Processing |access-date=2020-05-29}} (198 pages)</ref>

<ref name="Kudielka_1961">{{cite book |title=Extension of the Algorithmic Language ALGOL |chapter=2 |author-first1=Viktor |author-last1=Kudielka |author-first2=Peter |author-last2=Lucas |author-link2=Peter Lucas (computer scientist) |author-first3=Kurt |author-last3=Walk |author-first4=Kurt |author-last4=Bandat |author-first5=Heinz |author-last5=Bekic |author-first6=Heinrich "Heinz" Josef |author-last6=Zemanek |author-link6=Heinrich Josef Zemanek |type=Final Report |id=European Research Office Contract DA-91–591-EUC-1430 |date=1961-07-31}}</ref>

<ref name="Kudielka_1962">{{cite conference |editor-first1=Johannes |editor-last1=Dörr |editor-first2=Ernst Ferdinand |editor-last2=Peschl |editor-link2=Ernst Ferdinand Peschl |editor-first3=Heinz |editor-last3=Unger |editor-link3=:de:Heinz Unger (Mathematiker) |author-first=Viktor |author-last=Kudielka |book-title=2. Colloquium über Schaltkreis- und Schaltwerk-Theorie - Vortragsauszüge vom 18. bis 20. Oktober 1961 in Saarbrücken |title=Programmierung von Minimisierungsverfahren für zweistufige Logik |language=de |series=Internationale Schriftenreihe zur Numerischen Mathematik [International Series of Numerical Mathematics] (ISNM) |volume=4 |date=January 1963 |orig-date=1961-10-18 |edition=2013-12-20 reprint of 1st |___location=Institut für Angewandte Mathematik, [[Universität Saarbrücken]], Rheinisch-Westfälisches Institut für Instrumentelle Mathematik |publisher=[[Springer Basel AG]] / [[Birkhäuser Verlag Basel]] |isbn=978-3-0348-4081-1 <!-- |book-doi=10.1007/978-3-0348-4156-6 -->|doi=10.1007/978-3-0348-4156-6 |pages=49–65 |url=https://books.google.com/books?id=exCmBgAAQBAJ |chapter-url=https://link.springer.com/chapter/10.1007/978-3-0348-4156-6_2 |access-date=2020-04-15}} (152 pages)</ref>

<ref name="Wells_1962">{{cite conference |title=Chapter 14. Switching Theory: Application of a Finite Set Covering Theorem to the Simplification of Boolean Function Expressions |book-title=Information Processing, Proceedings of the 2nd IFIP Congress 1962, Munich, Germany, August 27 - September 1, 1962 |author-last=Wells |author-first=Mark B. |___location=Munich, Germany <!-- |chapter=Chapter 14: Switching Theory --> |date=1962 |publisher=[[North-Holland (publisher)|North-Holland]] |volume=2 |pages=731–735 |url=https://dblp.org/rec/conf/ifip/Wells62 |access-date=2020-05-28}}</ref>

<!-- TBD: Possibly also related: <ref name="Scheinman_1958">{{cite journal |title=A numerical-graphical method for synthesizing switching circuits |author-first=Arnold H. |author-last=Scheinman |journal=[[Transactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics]] |volume=76 |issue=6 |id=#34. Bell Lab Monograph No. 2979 |date=January 1958 |issn=0097-2452 |eissn=2379-674X |doi=10.1109/TCE.1958.6372729 |pages=687–689}}</ref> -->

<ref name="Scheinman_1962">{{cite journal |title=A Method For Simplifying Boolean Functions |author-first=Arnold H. |author-last=Scheinman<!-- "AHS" most probably a Bellcomm, Inc. employee in New York, also involved in NASA work (Apollo) --> |journal=[[Bell System Technical Journal]] |publisher=[[Nokia Bell Labs]] |volume=41 |issue=4 |date=July 1962 |orig-date=1962-03-06 |issn=0005-8580 |doi=10.1002/j.1538-7305.1962.tb03280.x |pages=1337–1346 |url=https://archive.org/details/bstj41-4-1337}} [https://archive.org/details/bstj41-4-1337] (NB. Also known as ''Scheinman's binary method'', this is an easy to use iterative method also for large functions, which will result in significantly simplified functions, but not necessarily in the simplest. The author is sometimes misspelled as "Schienmann".)</ref>

<ref name="Brown_2012">{{cite book |title=Boolean Reasoning - The Logic of Boolean Equations |author-first=Frank Markham |author-last=Brown |edition=<!-- 2012 -->reissue of 2nd |publisher=[[Dover Publications, Inc.]] |___location=Mineola, New York |date=2012 |orig-date=2003, 1990 |isbn=978-0-486-42785-0 |id={{ISBN|0-486-42785-4}}}} [<!-- 1st edition -->http://www2.fiit.stuba.sk/~kvasnicka/Free%20books/Brown_Boolean%20Reasoning.pdf First Edition PDF<!-- https://web.archive.org/web/20170416231752/http://www2.fiit.stuba.sk/~kvasnicka/Free%20books/Brown_Boolean%20Reasoning.pdf -->]</ref>

<ref name="Marquand_1881">{{cite journal |title=XXXIII: On Logical Diagrams for ''n'' terms |author-first=Allan |author-last=Marquand |author-link=Allan Marquand |journal=[[The London, Edinburgh, and Dublin Philosophical Magazine and Journal of Science]] |issue=75 |series=5 |date=1881 |volume=12 |doi=10.1080/14786448108627104 |pages=266–270}} (NB. Quite many secondary sources erroneously cite this work as "A logical diagram for ''n'' terms" or "On a logical diagram for ''n'' terms".)</ref>

<ref name="Veitch_1952">{{cite journal |author-last=Veitch |author-first=Edward Westbrook |author-link=Edward Westbrook Veitch |title=A Chart Method for Simplifying Truth Functions |journal=Transactions of the 1952 ACM Annual Meeting |series=ACM Annual Conference/Annual Meeting: Proceedings of the 1952 ACM Annual Meeting (Pittsburgh, Pennsylvania, USA) |___location=New York, USA |publisher=[[Association for Computing Machinery]] (ACM) |pages=127–133 |date=1952-05-03 |orig-date=1952-05-02 |doi=10.1145/609784.609801}}</ref>

<ref name="Svoboda_1955">{{cite book |title=Graphisch-mechanische Hilfsmittel für die Synthese von Relaisschaltungen |trans-title=Graphical-mechanical aids for the synthesis of relay circuits |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |publisher=Internationales Mathematiker-Kolloquium über aktuelle Probleme der Rechentechnik |type=Report |___location=Dresden, Germany |date=1955-11-27 |orig-date=1955-11-22 |pages=43–50<!-- some sources state 42–50 -->}} (NB. According to {{citeref|Constantinescu|1959|Constantinescu|style=plain}} the contents might be identical to a {{citeref|Svoboda|1956b|journal article|style=plain}} in 1956.)</ref>

<ref name="Svoboda_1956_1">{{cite conference |title=Graficko-mechanické pomůcky užívané při analyse a synthese kontaktových obvodů |language=cs |trans-title=Utilization of graphical-mechanical aids for the analysis and synthesis of contact circuits<!-- also as: Graphical-mechanical aids for the synthesis of relay circuits --> |periodical=<!-- |conference= -->Stroje na zpracování informací |trans-periodical=<!-- |trans-conference= -->Symposium on information processing machines |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |publisher=Czechoslovak Academy of Sciences, Research Institute of Mathematical Machines |___location=Prague |date=1956<!-- to override the |year=1956a display --> |year=1956a<!-- only for citeref --> |volume=IV |pages=9–22<!-- other sources state: 9–21 or 9–20 -->}}</ref>

<ref name="Svoboda_1956_2">{{cite book |title=(unknown) |trans-title=Graphical-Mechanical Aids for the Synthesis of Relay Circuits |language=cs |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |journal=[[Nachrichtentechnische Fachberichte]] (NTF), Beihefte der Nachrichtentechnischen Zeitschrift (NTZ) |publisher=[[Friedrich Vieweg & Sohn]] |___location=Braunschweig, Germany |date=1956<!-- to override the |year=1956b display --> |year=1956b<!-- only for citeref --> |volume=4 |pages=213–218 |id=ECIP55 213}} (NB. According to {{citeref|Constantinescu|1959|Constantinescu|style=plain}} the contents might be identical to a {{citeref|Svoboda|1955|congress report|style=plain}} in 1955.)</ref>

<ref name="Svoboda_1957">{{cite conference |title=Some Applications of Contact Grids |book-title=Proceedings of an International Symposium on the Theory of Switching, 2–5 April 1957, Part I |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |publisher=[[Harvard University Press]] |___location=Harvard University, Cambridge, Massachusetts, USA |series=The Annals of the Computation Laboratory of Harvard University |volume=XXIX |date=1959 |orig-date=1957-03-29 |pages=293–305}} (305 pages)</ref>

<ref name="Svoboda_1958">{{cite conference |title=(unknown) |trans-title=Graphical aids to minimization in switching circuits |language=cs |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |periodical=<!-- |conference= -->Stroje na zpracování informací |trans-periodical=<!-- |trans-conference= -->Symposium on information processing machines |volume=VI |publisher=Czechoslovak Academy of Sciences, Research Institute of Mathematical Machines |___location=Prague |date=1958 |pages=35–53}}</ref>

<ref name="McNaughton_1958">{{cite journal |title=Antonin Svoboda. Graphico-mechanical aids for the synthesis of relay circuits. Aktuelle Probleme der Rechentechnik, Deutscher Verlag der Wissenschaften, Berlin 1957, pp. 43–50. |author-first=Robert Forbes |author-last=McNaughton |author-link=Robert Forbes McNaughton, Jr. |journal=[[Journal of Symbolic Logic]] |volume=23 |issue=1 |date=March 1958 |language=en |type=Review |doi=10.2307/2964502 |pages=60–61 |url=https://www.cambridge.org/core/journals/journal-of-symbolic-logic/article/antonin-svoboda-graphicomechanical-aids-for-the-synthesis-of-relay-circuits-aktuelle-probleme-der-rechentechnik-deutscher-verlag-der-wissenschaften-berlin1957-pp-4350/8C379ABC629F4FD53569F7176DABA958 |access-date=2020-05-14 |quote-page=60 |quote=The two graphico-mechanical aids are contact bones and contact grids. Contact bones are an aid in analyzing (i.e., finding a logical formula for) contact networks. The logical theory of contact network analysis has been generally understood for a long time, but there are practical difficulties, especially in the analysis of bridge networks (i.e., networks which are not of the series-parallel type). Contact grids are an aid in obtaining a normal formula for functions given in truth-table form. They are helpful in obtaining what are called (by others) prime implicants. […]}} (NB. This review is about Svoboda's {{citeref|Svoboda|1955|congress report|style=plain}}.)</ref>

<ref name="Constantinescu_1959">{{cite journal |title=Svoboda, Antonin. Graphical-mechanical aids for the synthesis of relay circuits. Elektronische Rechenmaschinen und Informationsverarbeitung, 213–218 (1956). &mdash; Ber. Internat. Math.-Kolloquium Dresden, 22. bis 27. Nov. 1955, 42–50 (1957). |author-first=Paul |author-last=Constantinescu |journal=[[Zentralblatt für Mathematik]] |volume=82 |issue=1 |date=1959-12-22 |language=en |zbl=0082.12602 |type=Review |page=126 |url=https://zbmath.org/scans/082/126.gif |access-date=2020-05-14 |url-status=live |archive-url=https://web.archive.org/web/20200514124919/https://zbmath.org/scans/082/126.gif |archive-date=2020-05-14 |quote-page=126 |quote=The author utilizes interesting mechanical aids in solving problems concerning contact networks. The basis for the creation of these aids is the fact that each independent variable may be expressed by a Boolean sum of variables which define the state of the network. Employing "contact bones" and "contact grids" the author achieves the analysis and synthesis of a contact network and the transformation of the Boolean functions given in tabular form in algebraic form.}} (NB. This review is about Svoboda's {{citeref|Svoboda|1955|congress report|style=plain}} and {{citeref|Svoboda|1956b|journal article|style=plain}}.)</ref>

<ref name="Svoboda_1960">{{cite conference |title=Analysis of Boolean functions by logical punched-cards |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |date=1960 |periodical=<!-- |conference= -->Stroje na zpracování informací |trans-periodical=<!-- |trans-conference= -->Symposium on information processing machines |volume=VII |pages=13–20}}</ref>

<ref name="Svoboda_1961">{{cite journal |script-title=ru:Некоторые способы применения контактных сеток |trans-title=Some applications of contact grids |language=ru |script-journal=ru:[[Автоматика и Телемеханика]] |journal=[[Avtomatika i Telemekhanika]] |trans-journal=Automation and Remote Control <!-- |issn=0005-2310? 0005-1179? --> |author-first=Antonín [Антони́н] |author-last=Svoboda [Свобода] |author-link=Antonín Svoboda (computer scientist) |date=1961-02-02 |volume=XXII |issue=8 |id={{mathnet|at12365}} |pages=1061–1107 |url=http://www.mathnet.ru/links/f885d00d1502b9c89d252d5d078e8f3a/at12365.pdf |access-date=2020-05-16 |url-status=live |archive-url=https://web.archive.org/web/20200519043801/http://www.mathnet.ru/php/archive.phtml?wshow=paper&jrnid=at&paperid=12365&option_lang=rus |archive-date=2020-05-19}} [https://web.archive.org/web/20201230212854/http://www.mathnet.ru/links/a26f34b6ae77bd8aa6ca92703cfcf3bf/at12365.pdf] (11 pages)</ref>

<ref name="Svoboda_1969">{{cite journal |title=Logical Instruments for Teaching Logical Design |author-first=Antonín |author-last=Svoboda |author-link=Antonín Svoboda (computer scientist) |journal=[[IEEE Transactions on Education]] |publisher=[[IEEE]] |date=December 1969 |volume=E-12 |issue=4 |issn=0018-9359 |eissn=1557-9638 |doi=10.1109/TE.1969.4320517 |pages=262–273}}</ref>

<ref name="Svoboda_1979">{{cite book |title=Advanced Logical Circuit Design Techniques |author-first1=Antonín |author-last1=Svoboda |author-link1=Antonín Svoboda (computer scientist) |author-first2=Donnamaie E. |author-last2=White |date=2016 |orig-date=2012, 1985, 1979-08-01 |edition=retyped electronic reissue |publisher=[[Garland STPM Press]] (original issue) / WhitePubs Enterprises, Inc. (reissue) |lccn=78-31384 |isbn=0-8240-7014-3<!-- 1990 1st issue --> |id={{ISBN|978-0-8240-7014-4}}<!-- 1990 1st issue --> |url=http://www.donnamaie.com/Advanced_logic_ckt/Advanced_Logical_Circuit_Design_Techniques%20sm.pdf |access-date=2017-04-15 |url-status=live |archive-url=https://web.archive.org/web/20160315001009/http://donnamaie.com/Advanced_logic_ckt/Advanced_Logical_Circuit_Design_Techniques%20sm.pdf |archive-date=2016-03-15}} [http://www.donnamaie.com/<!-- https://web.archive.org/web/20170415220158/http://www.donnamaie.com/ -->][https://books.google.com/books?id=g3uzAAAAIAAJ]</ref>

<ref name="Klír_1968">{{cite book |title=Synthesis of Switching Circuits |author-first1=George Jiří |author-last1=Klír |author-link1=George Jiří Klír |author-first2=Lev K. |author-last2=Seidl |editor-first=W. A. |editor-last=Ainsworth |date=1968<!-- English edition --> |orig-date=1966<!-- original Czech edition --> |others=Translated by Dolan, Pavel |edition=1st English |publisher=[[Iliffe Books Ltd.]] / (SNTL Publishers of Technical Literature, Prague) |publication-place=London, UK |pages=62–66, 69–75, 199–204}} (325+1 pages)</ref>

<ref name="Roginskij_1983">{{cite journal |script-title=ru:Вадим Николаевич Рогинский (некролог) |language=ru |trans-title=Vadim Nikolaevich Roginsky (obituary) |journal=Problemy Peredachi Informatsii |script-journal=ru:Проблемы передачи информации |trans-journal=<!-- English edition with different ISSN: -->Problems of Information Transmission |date=1983 |volume=XIX |issue=3 |issn=0555-2923 |id={{mathnet|ppi1195}} |page=111 |url=http://mi.mathnet.ru/rus/ppi/v19/i3/p111 |access-date=2020-05-29 |url-status=live |archive-url=https://web.archive.org/web/20200529163228/http://www.mathnet.ru/php/archive.phtml?wshow=paper&jrnid=ppi&paperid=1195&option_lang=rus |archive-date=2020-05-29}} [https://web.archive.org/web/20201230205448/http://www.mathnet.ru/links/d09f622d3970d44faa3f152b46640633/ppi1195.pdf] (NB. The author's ({{GND|1157173993|1158776373}}) name is sometimes translated as "Vladimir Nikolaevič", "Wladimir Nikolajewitsch" and as "Roginsky", "Roginskiĭ", or "Roginski".)<!-- https://web.archive.org/web/20200530080915/https://www.computer-museum.ru/histsoft/gavrshar.htm A cartoon of Roginskij - possibly useful for a future article about him. --></ref>

<ref name="Roginskij_1957_1">{{cite journal |title=(unknown) |trans-title=Graphical method of synthesizing contact networks<!-- (Eine graphische Methode zur Synthese von Kontaktschaltungen) --> |language=ru |author-last=Roginskij [Рогинский] |author-first=Vadim Nikolaevich [Вадим Николаевич] |journal=Èlektrosvâzʹ |volume=XI |number=11 |date=1957 |issn=0013-5771<!-- ISSN assigned retrospectively --> |pages=82–88}}</ref>

<ref name="Roginskij_1957_2">{{cite conference |title=A graphical method for the synthesis of multi-terminal contact networks |title-link=:wikidata:Q28048673 |language=en |author-last=Roginskij [Рогинский] |author-first=Vadim Nikolaevich [Вадим Николаевич] |book-title=Proceedings of an International Symposium on the Theory of Switching, 2–5 April 1957, Part II |___location=Harvard University, Cambridge, Massachusetts, USA |date=1959 |orig-date=1957-03-29 |series=The Annals of the Computation Laboratory of Harvard University |volume=XXX |pages=302–315}} (345 pages) (NB. This is a translation of a Russian paper prepared for the symposium. Roginskij submitted the paper for presentation, but then could not attend personally. The translation was carried out by some of the American attendees<!-- must have been one of: Walter Vickery, Nicholas Vitt (of the Russian Research Center), Mark Pivovonsky, Anthony Oettinger, Peter Calingaert (of the Computation Laboratory). -->.)</ref>

<ref name="Roginskij_1958">{{cite journal |title=(unknown) |trans-title=Graphical method for synthesizing multi-terminal contact networks |language=ru |editor-last=Povarov [Поваров] |editor-first=Gellius Nikolaevich [Геллий Николаевич] |editor-link=:ru:Поваров, Геллий Николаевич |author-last=Roginskij [Рогинский] |author-first=Vadim Nikolaevich [Вадим Николаевич] |journal=Avtomatika<!-- also as: Avtomatyka --> |trans-journal=Automation |___location=Kiev |issn=0572-2691<!-- ISSN applied retrospectively --> |volume=3 |date=1958 |pages=84–91}}</ref>

<ref name="Roginskij_1962">{{cite book |title=Grundlagen der Struktursynthese von Relaisschaltungen |language=de |author-last=Roginskij [Рогинский] |author-first=Vadim Nikolaevich [Вадим Николаевич] |translator-first1=Albin |translator-last1=Hausenblas |translator-first2=Robert |translator-last2=Pfaffinger |translator-first3=H. |translator-last3=Resele |date=1962 |edition=1st German |publisher={{ill|Oldenbourg Verlag{{!}}R. Oldenbourg Verlag|de|R. Oldenbourg Verlag}} |publication-place=Munich, Germany |oclc=968499019 |id={{OCLC|163791522}} |url=https://books.google.com/books?id=TUkNzQEACAAJ |access-date=2002-05-30 |postscript=none}} (204 pages). This book is a translation of the original work: {{cite book |author-last=Roginskij [Рогинский] |author-first=Vadim Nikolaevich [Вадим Николаевич] |script-title=ru:Элементы структурного синтеза релейных схем управления |title=Ėlementy strukturnogo sinteza releĭnykh skhem upravlenii︠a︡ |language=ru |edition=1st |publisher=Изд-во Академии наук СССР (Izdatel'stvo akademii nauk SSSR) |___location=Moscow |date=1959 |editor-first=Aleksandr Aleksandrovich [Александр Александрович] |editor-last=Kharkevich [Харкевич] |editor-link=:ru:Харкевич, Александр Александрович |url=https://books.google.com/books?id=VTs4MwEACAAJ |postscript=none}} [https://books.google.com/books?id=ZbwWAAAAIAAJ]. Also available in English as: {{cite book |title=The Synthesis of Relay Switching Circuits |edition=1st English |language=en |author-last=Roginskij [Рогинский] |author-first=Vadim Nikolaevich [Вадим Николаевич] |translator-last=Chrzczonowicz |publisher=[[Van Nostrand Reinhold Inc.]] |___location=New York, USA |isbn=0-44207020-9 |date=1963}} (188 pages).</ref>

<ref name="Föllinger-Weber_1967">{{cite book |title=Methoden der Schaltalgebra |language=de |chapter=5.4. Die Methode der Harvard Group of Computation / 5.5 Vereinfachungsmethode nach Scheinman |author-first1=Otto |author-last1=Föllinger |author-link1=:de:Otto Föllinger |author-first2=Wolfgang |author-last2=Weber |date=1967 |orig-date=June 1965 |edition=1 |publisher={{ill|Oldenbourg Verlag{{!}}R. Oldenbourg Verlag|de|R. Oldenbourg Verlag}} |publication-place=Munich, Germany |___location=Frankfurt am Main, Germany |pages=103, 120, 122–128, 128–135}} (6+320+6 pages)</ref>

<ref name="Händler_1958">{{cite book |title=Ein Minimisierungsverfahren zur Synthese von Schaltkreisen (Minimisierungsgraphen) |language=de |author-first=Wolfgang |author-last=Händler |author-link=Wolfgang Händler |publisher=[[Technische Hochschule Darmstadt]] |___location=Potsdam, Germany |date=1958-12-19 |id=D&nbsp;17 |type=Dissertation |url=https://books.google.com/books?id=D58TAQAAIAAJ}} (73 pages+app.) [https://www.tib.eu/de/suchen/id/TIBKAT%3A044782241/Ein-Minimisierungsverfahren-zur-Synthese-von-Schaltkreisen/]</ref>

<ref name="Dokter_1973">{{cite book |title=Digital Electronics |author-first1=Folkert |author-last1=Dokter |author-first2=Jürgen |author-last2=Steinhauer |chapter=3.7.1. Händler's diagram |date=1973-06-18 |series=Philips Technical Library (PTL) / Macmillan Education |publisher=[[The Macmillan Press Ltd.]] / [[N. V. Philips' Gloeilampenfabrieken]] |edition=Reprint of 1st English |___location=Eindhoven, Netherlands |sbn=333-13360-9 |isbn=978-1-349-01419-4 |doi=10.1007/978-1-349-01417-0 |pages=108–111 |chapter-url=https://books.google.com/books?id=hlRdDwAAQBAJ&pg=PA108 |url=https://books.google.com/books?id=hlRdDwAAQBAJ |access-date=2020-05-11}} (270 pages) (NB. This is based on a translation of volume I of the two-volume German edition.)</ref>

<ref name="Dokter_1975">{{cite book |author-first1=Folkert |author-last1=Dokter |author-first2=Jürgen |author-last2=Steinhauer |title=Digitale Elektronik in der Meßtechnik und Datenverarbeitung: Theoretische Grundlagen und Schaltungstechnik |chapter=3.7.1. Kreisgraphen nach Händler |language=de |series=Philips Fachbücher |publisher=[[Deutsche Philips GmbH]] |publication-place=Hamburg, Germany |volume=I |date=1975 |orig-date=1969 |edition=improved and extended 5th |isbn=3-87145-272-6 |pages=115, 124, 129, 130–134 [130–134]}} (xii+327+3 pages) (NB. The German edition of volume I was published in 1969, 1971, two editions in 1972, and 1975. Volume II was published in 1970, 1972, 1973, and 1975.)</ref>

<ref name="Klar_1970">{{cite book |title=Digitale Rechenautomaten – Eine Einführung |language=de |trans-title=Digital Computers – An Introduction |chapter=2.4.2 Graphische Minimisierungsverfahren |trans-chapter=2.4.2 Graphical minimisation methods |author-first=Rainer |author-last=Klar |publisher=[[Walter de Gruyter & Co.]] / {{ill|G. J. Göschen'sche Verlagsbuchhandlung|de|G. J. Göschen’sche Verlagsbuchhandlung}} |publication-place=Berlin, Germany |series=Sammlung Göschen |volume=1241/1241a |date=1970-02-01 |isbn=3-11-083160-0 |id={{ISBN|978-3-11-083160-3}}. Archiv-Nr. 7990709. |pages=70–73 |edition=1 |url=https://books.google.com/books?id=QnqVDwAAQBAJ&pg=PA70 |access-date=2020-04-13 |url-status=live |archive-url=https://web.archive.org/web/20200413011211/https://books.google.com/books?id=QnqVDwAAQBAJ&pg=PA70 |archive-date=2020-04-13 |quote-pages=70–72 |quote=[…] Der Kreisgraph nach Händler ordnet den einzelnen [[Minterm]]en Knoten eines Graphen zu. Die Nachbarschaft von Mintermen wird durch Kanten dargestellt, die die entsprechenden Knoten miteinander verbinden. Bei dem "Kreisgraph" liegen sämtliche Knoten auf einem Kreis. Um symmetrische Kanten zu bekommen, wird die Reihenfolge der Knoten (bzw. Minterme) durch den [[reflected Gray code|reflektierten Gray-Code]] festgelegt, der sich durch fortlaufende Spiegelung und Ergänzung konstruieren läßt. Die negierten Variablen werden dabei durch Nullen, die nichtnegierten durch Einsen dargestellt. Man beginnt mit einer Variablen, die negiert (0) oder nichtnegiert (1) auftritt. Die 0 und 1 werden gespiegelt. Durch Anfügen einer Null vor 0 und 1 und einer Eins vor die Spiegelbilder werden Terme mit 2 Variablen gebildet. Die Spiegelung und das Anfügen von Nullen und Einsen wird wiederholt, bis die gewünschte Zahl von n Variablen und 2ⁿ Termen erreicht ist. […] Das Minimisierungsverfahren mit dem Kreisgraphen verläuft in folgenden Schritten: I. Aufstellung der DKF [disjunktive kanonische Form]. II. Alle Knoten, die auftretende Minterme repräsentieren, werden gekennzeichnet. III. Alle Kanten, die markierte Knoten verbinden, werden gekennzeichnet. Der so entstandene Untergraph markiert sämtliche [[prime implicant|Primimplikanten]]. Er setzt sich zusammen aus folgenden Unterstrukturen: isolierten Knoten (Primimplikant der Länge n), 2¹ verbundenen Knoten (Primimplikant der Länge n−1), 2² verbundenen Knoten (Primimplikant der Länge n−2), 2³ verbundenen Knoten (Primimplikant der Länge n−3) usw. Das Auffinden der wesentlichen Primimplikanten und der Restüberdeckung bleibt wie beim Karnaugh-Veitch-Diagramm der Geschicklichkeit überlassen. […]}} (205 pages) (NB. A 2019 reprint of the first edition is available under {{ISBN|3-11002793-3|978-3-11002793-8}}. A reworked and expanded {{citeref|Klar|1989|4th edition|style=plain}} exists as well.)</ref>

<ref name="Klar_1989">{{cite book |title=Digitale Rechenautomaten – Eine Einführung in die Struktur von Computerhardware |language=de |trans-title=Digital Computers – An Introduction into the structure of computer hardware |chapter=2.4.2 Graphische Minimisierungsverfahren |trans-chapter=2.4.2 Graphical minimisation methods |author-first=Rainer |author-last=Klar |publisher=[[Walter de Gruyter & Co.]] |publication-place=Berlin, Germany |series=Sammlung Göschen |volume=2050 |date=1989 |orig-date=1988-10-01 |isbn=3-11011700-2 |id={{ISBN|978-3-11011700-4}} |pages=94–97 |edition=4th reworked}} (320 pages)</ref>

<ref name="Hotz_1974">{{cite book |title=Schaltkreistheorie |language=de |trans-title=Switching circuit theory |author-first=Günter |author-last=Hotz |author-link=Günter Hotz |publisher=[[Walter de Gruyter & Co.]] |series=DeGruyter Lehrbuch |date=1974 |isbn=3-11-00-2050-5 |page=117 |edition=1 |url=https://books.google.com/books?id=VhmBDwAAQBAJ&pg=PA117 |access-date=2020-04-13 |url-status=live |archive-url=https://web.archive.org/web/20200413004433/https://books.google.com/books?id=VhmBDwAAQBAJ&pg=PA117&lpg=PA117#v=onepage&q&f=false |archive-date=2020-04-13 |quote-page=117 |quote=[…] Der Kreisgraph von ''[[Wolfgang Händler|Händler]]'' ist für das Auffinden von [[prime implicant|Primimplikanten]] gut brauchbar. Er hat den Nachteil, daß er schwierig zu zeichnen ist. Diesen Nachteil kann man allerdings durch die Verwendung von Schablonen verringern. […] |trans-quote=The circle graph by ''Händler'' is well suited to find [[prime implicant]]s. A disadvantage is that it is difficult to draw. This can be remedied using stencils.}}</ref>

<ref name="ISER_1">{{cite web |title=Informatik Sammlung Erlangen (ISER) |date=2012-03-13 |publisher=[[Friedrich-Alexander Universität]] |___location=Erlangen, Germany |language=de |url=https://www.rrze.fau.de/wir-ueber-uns/kooperationen/iser.shtml |access-date=2017-04-12 |url-status=dead |archive-url=https://web.archive.org/web/20170516154655/https://www.rrze.fau.de/wir-ueber-uns/kooperationen/iser.shtml |archive-date=2017-05-16}} (NB. Shows a picture of a {{lang|de|Kreisgraph}} by ''[[Wolfgang Händler|Händler]]''.)</ref>

<ref name="ISER_2">{{cite web |title=Informatik Sammlung Erlangen (ISER) - Impressum |date=2012-03-13 |publisher=[[Friedrich-Alexander Universität]] |___location=Erlangen, Germany |language=de |url=http://www.iser.uni-erlangen.de:80/index.php?ort_id=327&tree=0 |access-date=2017-04-15 |url-status=live |archive-url=https://web.archive.org/web/20120226004316/http://www.iser.uni-erlangen.de/index.php?ort_id=327&tree=0 |archive-date=2012-02-26}} (NB. Shows a picture of a {{lang|de|Kreisgraph}} by ''[[Wolfgang Händler|Händler]]''.)</ref>

<ref name="Broy_1990">{{cite book |title=Informatik und Mathematik |language=de |trans-title=Computer Sciences and Mathematics |chapter=Geschichte der Schaltalgebra |trans-chapter=History of circuit switching algebra |author-first=Heinrich "Heinz" Josef |author-last=Zemanek |author-link=Heinrich Josef Zemanek |editor-first=Manfred |editor-last=Broy |editor-link=Manfred Broy |orig-date=1990 |date=2013 |publisher=[[Springer-Verlag]] |isbn=9783642766770 |id={{ISBN|3642766773}} |pages=43–72 |url=https://books.google.com/books?id=y5GfBgAAQBAJ |quote-page=58 |quote=Einen Weg besonderer Art, der damals zu wenig beachtet wurde, wies [[Wolfgang Händler|W. Händler]] in seiner Dissertation […] mit einem Kreisdiagramm. […] |doi=10.1007/978-3-642-76677-0_3}} (NB. Collection of papers at a colloquium held at the [[Bayerische Akademie der Wissenschaften]], 1989-06-12/14, in honor of [[Friedrich L. Bauer]].)</ref>

<ref name="Bauer-Wirsing_1991">{{cite book |author-first1=Friedrich Ludwig |author-last1=Bauer |author-link1=Friedrich Ludwig Bauer |author-first2=Martin |author-last2=Wirsing |author-link2=Martin Wirsing |title=Elementare Aussagenlogik |publisher=[[Springer-Verlag]] |language=de |___location=Berlin / Heidelberg |date=March 1991 |isbn=3-540-52974-8 |id={{ISBN|978-3-540-52974-3}} |pages=54–56, 71, 112–113, 138–139 |url=https://books.google.com/books?id=Ff58BwAAQBAJ |quote-page=54 |quote=[…] handelt es sich um ein [[Wolfgang Händler|Händler]]-Diagramm […], mit den Würfelecken als Ecken eines 2^m-gons. […] Abb. […] zeigt auch Gegenstücke für andere Dimensionen. Durch waagerechte Linien sind dabei Tupel verbunden, die sich nur in der ersten Komponente unterscheiden; durch senkrechte Linien solche, die sich nur in der zweiten Komponente unterscheiden; durch 45°-Linien und 135°-Linien solche, die sich nur in der dritten Komponente unterscheiden usw. Als Nachteil der Händler-Diagramme wird angeführt, daß sie viel Platz beanspruchen. […]}}</ref>

<ref name="Colloquium_1960">{{cite book |editor-first1=Ernst Ferdinand |editor-last1=Peschl |editor-link1=Ernst Ferdinand Peschl |editor-first2=Heinz |editor-last2=Unger |editor-link2=:de:Heinz Unger (Mathematiker) |title=Colloquium über Schaltkreis- und Schaltwerk-Theorie - Vortragsauszüge vom 26. bis 28. Oktober 1960 in Bonn |volume=3 |series=Internationale Schriftenreihe zur Numerischen Mathematik [International Series of Numerical Mathematics] (ISNM) |language=de |chapter=Zum Gebrauch von Graphen in der Schaltkreis- und Schaltwerktheorie |author-first=Wolfgang |author-last=Händler |author-link=Wolfgang Händler |___location=Institut für Angewandte Mathematik, [[Universität Saarbrücken]], Rheinisch-Westfälisches Institut für Instrumentelle Mathematik |publisher=[[Springer Basel AG]] / [[Birkhäuser Verlag Basel]] |date=2013 |orig-date=June 1961, 1960-10-26 |isbn=978-3-0348-5771-0 |id={{ISBN|3-0348-5771-3}} |doi=10.1007/978-3-0348-5770-3_10 |url=https://books.google.com/books?id=myTnoAEACAAJ |pages=169–198}} (198 pages)</ref>

<ref name="Kortum_1965_12">{{cite journal |title=Minimierung von Kontaktschaltungen durch Kombination von Kürzungsverfahren und Graphenmethoden |trans-title=Minimization of contact circuits by combination of reduction procedures and graphical methods |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=messen-steuern-regeln (msr) |language=de |publisher={{ill|Verlag Technik{{!}}VEB Verlag Technik|de|VEB Verlag Technik}} |publication-place=Berlin / Leipzig, Germany |date=1965 |volume=8 |issue=12 |pages=421–425 |issn=0026-0347 |id={{CODEN|MSRGAN|MSRGA|MMSRD}}. {{DNB-IDN|01269357X}}. {{ZDB|512087-1}} |oclc=310970250 |url=https://www.tib.eu/en/search/id/ei-backfile%3Ac84_64eb63f914c231eeM6f1319817173212/Minimization-of-contact-circuits-by-combination/ |access-date=2020-11-04}} (5 pages)</ref>

<ref name="Kortum_1966_1">{{cite journal |title=Konstruktion und Minimierung von Halbleiterschaltnetzwerken mittels Graphentransformation |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=messen-steuern-regeln (msr) |language=de |publisher={{ill|Verlag Technik{{!}}VEB Verlag Technik|de|VEB Verlag Technik}} |publication-place=Berlin / Leipzig, Germany |date=1966 |volume=9 |issue=1 |pages=9–12 |issn=0026-0347 |id={{CODEN|MSRGAN|MSRGA|MMSRD}}. {{DNB-IDN|01269357X}}. {{ZDB|512087-1}} |oclc=310970250 |url=https://www.tib.eu/en/search/id/ceaba%3ACEAB1966002519/KONSTRUKTION-UND-MINIMIERUNG-VON-HALBLEITER-SCHALTNETZWERKEN/ |access-date=2018-06-17 |url-status=usurped}}</ref>

<ref name="Kortum_1966_3">{{cite journal |title=Weitere Bemerkungen zur Minimierung von Schaltnetzwerken mittels Graphenmethoden |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=messen-steuern-regeln (msr) |language=de |publisher={{ill|Verlag Technik{{!}}VEB Verlag Technik|de|VEB Verlag Technik}} |publication-place=Berlin / Leipzig, Germany |date=1966 |volume=9 |issue=3 |pages=96–102 |issn=0026-0347 |id={{CODEN|MSRGAN|MSRGA|MMSRD}}. {{DNB-IDN|01269357X}}. {{ZDB|512087-1}} |oclc=310970250 |url=https://www.tib.eu/en/search/id/ceaba%3ACEAB1966002896/WEITERE-BEMERKUNGEN-ZUR-MINIMIERUNG-VON-SCHALTNETZWERKEN/ |access-date=2018-06-17 |url-status=usurped}}</ref>

<ref name="Kortum_1965_5"> {{cite journal |title=Weitere Bemerkungen zur Behandlung von Schaltnetzwerken mittels Graphen |trans-title=Further remarks on treatment of switching networks by means of graphs |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=Regelungstechnik |language=de |series=10. Internationales Wissenschaftliches Kolloquium. [10th international scientific colloquium] |publisher=[[Technische Hochschule Ilmenau]] |type=Conference paper |date=1965 |volume=10 |issue=5 |pages=33–39 |url=https://www.tib.eu/en/search/id/ei-backfile%3Ac84_a3574af8cb8d6293M72eb19817173212/Further-remarks-on-treatment-of-switching-networks/ |access-date=2020-11-04 |postscript=none}} (7 pages); {{cite journal |title=Weitere Bemerkungen zur Behandlung von Schaltnetzwerken mittels Graphen. Konstruktion von vermaschten Netzwerken (Brückenschaltungen) |trans-title=Further remarks on treatment of switching networks by means of graphs |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=messen-steuern-regeln (msr) |language=de |publisher={{ill|Verlag Technik{{!}}VEB Verlag Technik|de|VEB Verlag Technik}} |publication-place=Berlin / Leipzig, Germany |date=1966 |volume=9 |issue=5 |pages=151–157 |issn=0026-0347 |id={{CODEN|MSRGAN|MSRGA|MMSRD}}. {{DNB-IDN|01269357X}}. {{ZDB|512087-1}} |oclc=310970250}}</ref>

<ref name="Kortum_1966_12">{{cite journal |title=Zur Minimierung von Schaltsystemen |trans-title=Minimization of switching circuits |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=Wissenschaftliche Zeitschrift der TU Ilmenau |___location=Jena, Germany |language=de |publisher=Technische Hochschule für Elektrotechnik Ilmenau / Forschungsstelle für Meßtechnik und Automatisierung der Deutschen Akademie der Wissenschaften |date=1966 |orig-date=1965 |volume=12 |issue=2<!-- one sources states: 2, 3. --> |pages=181–186 |url=https://www.tib.eu/en/search/id/ei-backfile%3Ac84_125e37df8f0a3cd4eM7a8919817173212/Minimization-of-switching-circuits/ |access-date=2020-11-04}} (6 pages)</ref>

<ref name="Kortum_1967_6">{{cite journal |title=Über zweckmäßige Anpassung der Graphenstruktur diskreter Systeme an vorgegebene Aufgabenstellungen |author-first=Herbert Franz |author-last=Kortum |author-link=:de:Herbert Kortum |journal=messen-steuern-regeln (msr) |language=de |publisher={{ill|Verlag Technik{{!}}VEB Verlag Technik|de|VEB Verlag Technik}} |publication-place=Berlin / Leipzig, Germany |date=1967 |volume=10 |issue=6 |pages=208–211 |issn=0026-0347 |id={{CODEN|MSRGAN|MSRGA|MMSRD}}. {{DNB-IDN|01269357X}}. {{ZDB|512087-1}} |oclc=310970250}}</ref>

<ref name="Tafel_1971">{{cite book |title=Einführung in die digitale Datenverarbeitung |language=de |trans-title=Introduction to digital information processing |chapter=4.3.5. Graphenmethode zur Vereinfachung von Schaltfunktionen |author-first=Hans Jörg |author-last=Tafel |publisher=[[Carl Hanser Verlag]] |date=1971 |___location=[[RWTH]], Aachen, Germany |publication-place=Munich, Germany |isbn=3-446-10569-7 |pages=98–105, 107–113}}</ref>

<ref name="Steinbuch-Wagner_1967">{{cite book |title=Taschenbuch der Nachrichtenverarbeitung |language=de |editor-first1=Karl W. |editor-last1=Steinbuch |editor-link1=Karl W. Steinbuch |editor-first2=Siegfried W. |editor-last2=Wagner |author-first1=Erich R. |author-last1=Berger |author-first2=Wolfgang |author-last2=Händler |author-link2=Wolfgang Händler |date=1967 |orig-date=1962 |edition=2 |publisher=[[Springer-Verlag OHG]] |___location=Berlin, Germany |id=Title No. 1036 |lccn=67-21079 |pages=64, 1034–1035, 1036, 1038 |quote-page=64 |quote=[…] Übersichtlich ist die Darstellung nach ''[[Wolfgang Händler|Händler]]'', die sämtliche Punkte, numeriert nach dem ''[[Gray-Code]]'' […], auf dem Umfeld eines Kreises anordnet. Sie erfordert allerdings sehr viel Platz. […] |trans-quote=''Händler's'' illustration, where all points, numbered according to the ''[[Gray code]]'', are arranged on the circumference of a circle, is easily comprehensible. It needs, however, a lot of space.}}</ref>

<ref name="Steinbuch-Weber_1974">{{cite book |title=Taschenbuch der Informatik - Band II - Struktur und Programmierung von EDV-Systemen |language=de |editor-first1=Karl W. |editor-last1=Steinbuch |editor-link1=Karl W. Steinbuch |editor-first2=Wolfgang |editor-last2=Weber <!-- |editor-link2=:de:Wolfgang Weber (Ingenieur)? --> |editor-first3=Traute |editor-last3=Heinemann |date=1974 |orig-date=1967 |edition=3 |volume=2 |work=Taschenbuch der Nachrichtenverarbeitung |publisher=[[Springer-Verlag]] |___location=Berlin, Germany |isbn=3-540-06241-6 |lccn=73-80607 |pages=25, 62, 96, 122–123, 238}}</ref>

<ref name="Axmann_1979">{{cite book |title=Einführung in die technische Informatik: Funktionsweise digitaler Bausteine und deren Verwendung in Datenerfassungssystemen |language=de |author-first=Hans-Peter |author-last=Axmann |publisher=[[Springer-Verlag Wien GmbH]] |date=2019 |orig-date=1979-06-13 |edition=reprint of 1st |isbn=978-3-211-81546-5 |doi=10.1007/978-3-7091-4478-7 |page=37 |url=https://books.google.com/books?id=1ZynDwAAQBAJ&pg=PA37 |access-date=2020-04-15 |quote-page=37 |quote=[…] Die Graphenmethode zur Vereinfachung von Schaltfunktionen zeichnet sich durch besondere Anschaulichkeit und Einfachheit aus. Sie ist dann besonders vorteilhaft, wenn die Schaltfunktion unter Verwendung bestimmter Verknüpfungsglieder mit minimalem Aufwand an Bauelementen und Verbindungsleitungen zu realisieren ist. Sie ist anderen Methoden, besonders bei der Netzwerksynthese von Brückenschaltungen wie auch bei der Optimierung von Kontaktschaltungen mit Sperrdioden, überlegen. Die erfolgreiche Anwendung der Graphenmethode setzt voraus, daß die vorgegebene Funktion bereits in einer weitgehend vereinfachten Form vorliegt, da mit dieser Methode Redundanzen nur noch sehr schwer zu eliminieren sind. […]}} (290 pages)</ref>

<ref name="Nelson_1955_1">{{cite journal |title=Simplest Normal Truth Functions |author-first=Raymond J. |author-last=Nelson |journal=[[Journal of Symbolic Logic]] |publisher=[[Association for Symbolic Logic]] |doi=10.2307/2266893 |jstor=2266893 |volume=20 |number=2 |date=June 1955 |pages=105–108}} (4 pages) (NB. A method converting a [[conjunctive normal form]] into a [[disjunctive normal form]], followed by a procedure similar to [[Willard Van Orman Quine|Quine]]'s.)</ref>

<ref name="Nelson_1955_2">{{cite journal |title=Weak Simplest Normal Truth Functions |author-first=Raymond J. |author-last=Nelson |journal=[[Journal of Symbolic Logic]] |publisher=[[Association for Symbolic Logic]] |volume=20 |number=3 |date=September 1955 |doi=10.2307/2268219 |jstor=2268219 |pages=232–234}} (3 pages)</ref>

<ref name="Lipp_2011">{{cite book |title=Grundlagen der Digitaltechnik |language=de |author-first1=Hans Martin |author-last1=Lipp |author-first2=Jürgen |author-last2=Becker |publisher={{ill|Oldenbourg Verlag{{!}}Oldenbourg Wissenschaftsverlag GmbH|de|Oldenbourg Wissenschaftsverlag}} / [[Walter de Gruyter]] |publication-place=Munich, Germany |date=2011 |isbn=9783486706932 |id={{ISBN|3486706934}} |edition=reworked 7th |url=https://books.google.com/books?id=xinpBQAAQBAJ |access-date=2020-05-12}} (316 pages)</ref>

<ref name="Riznyk_2017">{{cite journal |title=Minimization of Boolean functions by combinatorial method |language=en, ru |author-first1=Volodymyr |author-last1=Riznyk |author-first2=Mykhailo |author-last2=Solomko |date=July 2017 |journal=Information and Control Systems: Mathematical Modeling |issn=2226-3780 |id=UDC 681.325 |doi=10.15587/2312-8372.2017.108532 |volume=4/2 |issue=36 |pages=49–64 |url=https://www.researchgate.net/publication/320254030_Minimization_of_Boolean_functions_by_combinatorial_method |access-date=2020-05-12 |url-status=live |archive-url=https://web.archive.org/web/20200512211754/https://www.researchgate.net/publication/320254030_Minimization_of_Boolean_functions_by_combinatorial_method/fulltext/59d787afa6fdcc52acae795c/Minimization-of-Boolean-functions-by-combinatorial-method.pdf |archive-date=2020-05-12 |doi-access=free}}</ref>

<ref name="Riznyk_2018">{{cite journal |title=Minimization of Conductive Normal Forms of Boolean Functions by Combinatorial Method |language=en, ru |author-first1=Volodymyr |author-last1=Riznyk |author-first2=Mykhailo |author-last2=Solomko |date=July 2018 |journal=Information and Control Systems: Mathematical Modeling |issn=2226-3780 |id=UDC 681.325 |doi=10.15587/2312-8372.2018.146312 |doi-access=free |volume=5/2 |issue=43 |pages=42–55 |url=https://www.researchgate.net/publication/329722830_Minimization_of_conjunctive_normal_forms_of_boolean_functions_by_combinatorial_method/fulltext/5c18761aa6fdcc494ffc7648/Minimization-of-conjunctive-normal-forms-of-boolean-functions-by-combinatorial-method.pdf |access-date=2020-05-12 |url-status=live |archive-url=https://web.archive.org/web/20200512211953/https://www.researchgate.net/publication/329722830_Minimization_of_conjunctive_normal_forms_of_boolean_functions_by_combinatorial_method/fulltext/5c18761aa6fdcc494ffc7648/Minimization-of-conjunctive-normal-forms-of-boolean-functions-by-combinatorial-method.pdf |archive-date=2020-05-12}}</ref>

<ref name="Westphal_2001">{{cite web |title=Devices and techniques for logical processing |author-first=Jonathan |author-last=Westphal |author-link=Jonathan Westphal |id=Patent US7254304B2 |date=2007-08-07 |orig-date=2001-10-05, 2000-10-06 |url=https://patentimages.storage.googleapis.com/b9/bb/54/d1b35a744fc58a/US7254304.pdf |access-date=2020-05-09 |url-status=live |archive-url=https://web.archive.org/web/20200509174222/https://patentimages.storage.googleapis.com/b9/bb/54/d1b35a744fc58a/US7254304.pdf |archive-date=2020-05-09}} [https://patents.google.com/patent/US7254304] (77 pages)</ref>

<ref name="Westphal_2005">{{cite journal |title=Logic as a Vector System |author-first1=Jonathan |author-last1=Westphal |author-link1=Jonathan Westphal |author-first2=Jim |author-last2=Hardy |journal=[[Journal of Logic and Computation]] |publisher=[[Oxford University Press]] |volume=15 |issue=5 |date=2005-10-01 |orig-date=2004-02-16 |___location=[[Idaho State University]], Pocatello, Idaho, USA |pages=751–765 |doi=10.1093/logcom/exi040 |url=https://www.researchgate.net/publication/31374079_Logic_as_a_Vector_System |access-date=2020-05-09 |url-status=live |archive-url=https://web.archive.org/web/20200509200329/https://www.researchgate.net/publication/31374079_Logic_as_a_Vector_System |archive-date=2020-05-09}} [https://www.researchgate.net/profile/Jonathan_Westphal/publication/31374079_Logic_as_a_Vector_System/links/555f973908ae9963a118b4b7/Logic-as-a-Vector-System.pdf] (15 pages)</ref>

<ref name="Amaru_2014">{{cite journal |title=Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization |author-first1=Luca |author-last1=Amarú |author-first2=Pierre-Emmanuel |author-last2=Gaillardon |author-first3=Giovanni |author-last3=De Micheli |author-link3=Giovanni De Micheli |pages=1–6 |date=2014-05-05 |orig-date=2014-05-01 |journal=Proceedings of the 51st Annual Design Automation Conference (DAC) |publisher=[[Association for Computing Machinery]] (ACM) |doi=10.1145/2593069.2593158 |publication-place=San Francisco, California, USA |___location=Switzerland |url=https://dl.acm.org/doi/pdf/10.1145/2593069.2593158 |access-date=2020-05-09 |url-status=live |archive-url=https://web.archive.org/web/20200509164533/https://dl.acm.org/doi/pdf/10.1145/2593069.2593158 |archive-date=2020-05-09}} (6 pages)</ref>

<ref name="Amaru_2016">{{cite journal |title=Majority-Inverter Graph: A novel data-structure and algorithms for efficient logic optimization<!-- Majority-Inverter Graph: A New Paradigm for Logic Optimization --> |author-first1=Luca |author-last1=Amarú |author-first2=Pierre-Emmanuel |author-last2=Gaillardon |author-first3=Giovanni |author-last3=De Micheli |author-link3=Giovanni De Micheli |journal=[[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems]] |volume=35 |number=5 |date=2016 |publisher=[[IEEE]] |issn=0738-100X |isbn=978-1-4799-3017-3 |doi=10.1145/2593069.2593158 |publication-place=San Francisco, California, USA |___location=Switzerland |pages=806–819 |url=https://ieeexplore.ieee.org/abstract/document/6881521/authors#authors |access-date=2020-05-09}} (14 pages)</ref>

<ref name="Pandit_2017">{{cite journal |title=A Novel Graphical Technique for Combinational Logic Representation and Optimization |author-first1=Vedhas |author-last1=Pandit |author-first2=Björn Wolfgang |author-last2=Schuller |author-link2=Björn Wolfgang Schuller |date=2017-12-31 |orig-date=2017-11-14, 2017-10-11, 2017-05-05 |editor-first=Michele |editor-last=Scarpiniti |volume=2017 |number=5 |pages=1–12 |id=Article ID 9696342 |doi=10.1155/2017/9696342 |doi-access=free |journal=[[Complexity (journal)|Complexity]] |publisher=[[Hindawi Publishing Corporation]] / [[John Wiley & Sons, Inc.]] |issn=1076-2787 |eissn=1099-0526 |url=http://downloads.hindawi.com/journals/complexity/2017/9696342.pdf |access-date=2020-05-09 |url-status=live |archive-url=https://web.archive.org/web/20200509154342/http://downloads.hindawi.com/journals/complexity/2017/9696342.pdf |archive-date=2020-05-09}} (12 pages)</ref>

<ref name="Winkler_2013">{{cite web |title=Die Oprema – der Relaisrechner des Zeisswerks Jena |language=de |author-first=Jürgen F. H. |author-last=Winkler |___location=[[Friedrich Schiller University Jena|Friedrich Schiller University]], Jena, Germany |date=2013-04-07 |orig-date=2008-10-25 |pages=1–27 |type=Lecture notes |url=http://psc.informatik.uni-jena.de/publ/oprema-JW-2008.pdf |url-status=dead |archive-url=https://web.archive.org/web/20170830053343/http://psc.informatik.uni-jena.de/publ/oprema-JW-2008.pdf |archive-date=2017-08-30}} (27 pages)</ref>

<ref name="Winkler_2019">{{cite web |title=Oprema – The Relay Computer of Carl Zeiss Jena |author-first=Jürgen F. H. |author-last=Winkler |___location=[[Friedrich Schiller University Jena|Friedrich Schiller University]], Jena, Germany |date=2019-08-26 |orig-date=2014-10-25 |arxiv=1908.09549 |version=1 |pages=1–33 |url=https://arxiv.org/ftp/arxiv/papers/1908/1908.09549.pdf |access-date=2020-11-04 |url-status=live |archive-url=https://web.archive.org/web/20200929093823/https://arxiv.org/ftp/arxiv/papers/1908/1908.09549.pdf |archive-date=2020-09-29}} (33 pages)</ref>

<ref name="Burgoon_1972">{{cite magazine |title=Improve your Karnaugh mapping skills. Use of variables allows you to simplify maps and design circuits for latching or sequential-signal gating. |magazine=[[Electronic Design (magazine)|Electronic Design]] - For Engineers and Engineering Managers |issn=0013-4872 |author-first=J. Robert "Rob" |author-last=Burgoon<!-- https://web.archive.org/web/20210331201530/https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1981-03.pdf --> |___location=Hewlett-Packard, Santa Clara Division, Santa Clara, California, USA |volume=20 |number=26 |date=1972-12-21 |publisher=[[Hayden Publishing Company, Inc.]] |publication-place=Rochelle Park, New Jersey, USA |pages=54–56 |url=http://bitsavers.org/magazines/Electronic_Design/Electronic_Design_V20_N26_19721221.pdf |access-date=2021-02-14 |url-status=live |archive-url=https://web.archive.org/web/20210214194556/http://bitsavers.org/magazines/Electronic_Design/Electronic_Design_V20_N26_19721221.pdf |archive-date=2021-02-14}} (3 pages) (NB. A slight extension of this method by Larry L. Dornhoff is discussed in {{citeref|Muroga|1979|Muroga|style=plain}}.)</ref>

<ref name="Schultz_1969_1">{{anchor|Schultz-1969-1}}{{cite magazine |title=An Algorithm for the Synthesis of Complex Sequential Networks |author-first=G. W. |author-last=Schultz |magazine=Computer Design |issn=0010-4566 |id={{CODEN|CMPDA}} |oclc=828863003 |publisher=Computer Design Publishing Corporation |publication-place=Concord, Massachusetts, USA |___location=Central Data Systems, Inc., Sunnyvale, California, USA |volume=8 |issue=3 |date=March 1969 |pages=49–55 |url=https://books.google.com/books?id=Uy4-AQAAIAAJ&dq=%22infrequent+variable%22+karnaugh&focus=searchwithinvolume&q=%22An+Algorithm+for+the+Synthesis+of+Complex+Sequential+Networks%22 |access-date=2021-02-22}} (7 pages) (NB. This article caused a number of letters to the editor in [[#Schultz-1969-2|subsequent issues]] of the magazine.)</ref>

<ref name="Schultz_1969_2">{{anchor|Schultz-1969-2}}{{cite magazine |title=To the Editor |department=Letters to the editor |author-first=G. W. |author-last=Schultz |magazine=Computer Design |issn=0010-4566 |id={{CODEN|CMPDA}} |oclc=828863003 |publisher=Computer Design Publishing Corporation |publication-place=Concord, Massachusetts, USA |___location=Central Data Systems, Inc., Sunnyvale, California, USA |volume=8 |issue=5–12?<!-- must be in one of these --> |date=<!-- May or later? --> 1969 |page=10 |url=https://books.google.com/books?redir_esc=y&id=Uy4-AQAAIAAJ&dq=%22infrequent+variable%22+karnaugh&focus=searchwithinvolume&q=In+your+April+issue+you |quote-page=10 |quote=[…] In your April issue you published a {{citeref|Dineley|1969|letter by R. L. Dineley|style=plain}} describing a simple method for treating [[product-of-sums]] logical expressions. […] An even simpler method is taught by [[David A. Huffman|D. A. Huffman]]. This method is based on recognizing that the [[Boolean expression]] will be zero when any of the factors in the product-of-sums form is zero. Plotting zeroes of factors on a [[Veitch diagram]] or [[Karnaugh map]] is as easy as locating ones for a [[sum-of-product]]s expression. […] To illustrate, using Dineley's example (A+BC)(A+C): […] The zeroes resulting from A+BC will be located wherever both A and BC are zero. Therefore we locate on the map the expression <span style="text-decoration:overline">A</span>*<span style="text-decoration:overline">BC</span> (which is equal to <span style="text-decoration:overline">A</span>*<span style="text-decoration:overline">B</span> + <span style="text-decoration:overline">A</span>*<span style="text-decoration:overline">C</span>). Similarly the zeroes of A+C are located and plotted at <span style="text-decoration:overline">A</span>*<span style="text-decoration:overline">C</span>. With all zeroes located, the rest of the map can be filled with ones. One can be a little more formal and work out algebraically the [[logical complement]] of the expression under consideration and then plot zeroes for that resulting expression. In a simple product-of-sums representation, however, the complementary terms can be written by inspection; or the zeroes can be plotted by inspection without writing the complete expression […] "Classical Reduction Involving Infrequently Used Variables" October 11, 1968. [[University of Santa Clara]] […] Mr. [[Tom Osborne (engineer)|Osborne]]'s work draws close similarity to that I presented in [[#Schultz-1969-1|this article]] and thus, would certainly be of interest to those readers seeking further information. I understand he has done work to apply the technique of infrequent variables to the design of [[sequential network]]s constructed from [[Read Only Memory]]. Since he has not yet published anything on this area, if readers would like additional information, they can write Mr. Osborne at: […] Thomas E. Osborne […] Building 1U […] 1501 Page Mill Road […] Palo Alto, California […] Thank you for the opportunity to publish with you. […] G. W. Schultz […] Central Data Systems, Inc. […] Sunnyvale, Calif.}} (1 page) (NB. Osborne's method was later published by Clare.{{citeref|Clare|1971|B}})</ref>

<ref name="Langdon_1974">{{cite book |title=Logic Design - A Review of Theory and Practice |chapter=Chapter 4. Interrelationships, D. Logic Design and Switching Theory, 3. The Flow Table as a Point of Departure for Design |author-first=Glen G. |author-last=Langdon, Jr. |___location=IBM Corporation, San Jose, California, USA |editor-first=Robert "Bob" Lovett |editor-last=Ashenhurst |editor-link=:d:Q102124175 |date=1974 |edition=1 |series=ACM Monograph Series |publisher=[[Academic Press, Inc.]] - A Subsidiary of [[Harcourt Brace Jovanovich, Publishers]] |publication-place=New York, USA |isbn=0-12-436550-7 |lccn=73-18988 |issn=0572-4252 |id={{ISBN|978-0-12-436550-6}} |page=149 |url=https://books.google.com/books?id=sQwE8Gpsj5EC&pg=PA149 |access-date=2021-04-17 |url-status=live |archive-url=https://web.archive.org/web/20210417063924/https://books.google.de/books?id=sQwE8Gpsj5EC&pg=PA149 |archive-date=2021-04-17 |quote-page=149 |quote=[…] An important contribution to the adaptation of theory to practice was made by Schultz [[#Schultz-1969-1|[20]]]; he draws upon the designer's basic understanding of the problem and requires him to identify the "infrequent variables." Loosely defined, these variables do not relate to all internal states, i.e., they are not needed to define every state. In essence, the infrequent variables are relevant to only a few (perhaps one or two) states or state transitions. Schultz suggests that the designer first translate the verbal problem to a state transition graph that is reduced. The internal states are encoded and then information regarding infrequent variables is added to the appropriate state transitions. A "first approximation" to flip-flop input equations is made, based only upon the frequent variables. Schultz demonstrates how these equations can subsequently be modified to incorporate transitions controlled by the infrequent variables. In Schultz's examples the infrequent variables are all input signals, but this idea also applies to internal state variable signals that may be considered "infrequent." In this case, for example, an infrequent internal state variable flip-flop might be set by a particular circumstance and reset sometime later. The output of the flip-flop may now be treated as an infrequent input variable. […]}} (ix+1+179+3 pages)</ref>

<ref name="Clare_1970">{{cite book |title=Logic Design of Algorithmic State Machines |author-first=Christopher "Chris" R. |author-last=Clare |publisher=[[Hewlett-Packard]] |___location=Hewlett-Packard Laboratories, USA |date=February 1971 |orig-date=November 1970 |id={{CHMID|102650285}}}} (110 pages) [https://web.archive.org/web/20210217095629/https://www.computerhistory.org/collections/catalog/102650285] (NB. Several internal revisions existed in 1970 and 1971. This was later published by McGraw-Hill.{{citeref|Clare|1973|A}} [[Tom Osborne (engineer)|Thomas E. Osborne]]'s simplification method was already mentioned by [[#Schultz-1969-2|G. W. Schultz]] in 1969.)</ref>

<ref name="Clare_1973">{{cite book |title=Designing Logic Systems Using State Machines |chapter=Reducing the Required Map Size with Map-Entered Variables |author-first=Christopher "Chris" R. |author-last=Clare |others=[[Tom Osborne (engineer)|Osborne, Thomas "Tom" E.]] (initial contributions) |___location=Electronics Research Laboratory, Hewlett-Packard Laboratories |publisher=[[McGraw-Hill, Inc.]] |date=1973 |orig-date=November 1972 |edition=1 |isbn=0-07011120-0 |id={{ISBN|978-0-07011120-2}}. ark:/13960/t9383kw8n.<!-- archive.org: designinglogicsystemsusingstatemachines --> 79876543 |sbn=07-011120-0 |s2cid=60509061 |pages=41–42 |url=https://archive.org/details/designinglogicsystemsusingstatemachines |access-date=2021-02-14}} (2 pages of vii+114+3 pages) [https://archive.org/details/designinglogicsystemsusingstatemachines] (NB. This book is based on a 1970 Hewlett-Packard in-house document.{{citeref|Clare|1971|B}} A slight extension of this method by Larry L. Dornhoff is discussed in {{citeref|Muroga|1979|Muroga|style=plain}}.)</ref>

<ref name="Muroga_1979">{{cite book |title=Logic Design and Switching Theory |author-last=Muroga |author-first=Saburo |date=1979 |publisher=[[John Wiley and Sons, Inc.]] |publication-place=New York, USA |edition=1 |pages=161–163 |isbn=0-47104418-0 |id={{ISBN|978-0-47104418-5}} |url=https://books.google.com/books?id=dAtTAAAAMAAJ}} (3 pages of 617 pages); {{cite book |title=Logic Design and Switching Theory |author-last=Muroga |author-first=Saburo |date=January 1990 |orig-date=1979 |edition=updated reprint |publisher=Robert E. Krieger Publishing Company, Inc. |lccn=90-32076 |publication-place=Malabar, Florida, USA |isbn=0-89464-463-7 |pages=161–163}} (617+5-6+32 pages) (NB. Original chapters 6.3–6.6 (pages 281–320) were replaced by new chapters 6.3–6.5 (inserted pages 1–32); also in 1997 under {{ISBN|1-57524036-X|978-1-57524036-7}}. The method described here is a slight extension by Larry L. Dornhoff of the method discussed in {{citeref|Burgoon|1972|Burgoon|style=plain}} and {{citeref|Clare|1973|Clare|style=plain}}. A further extension of this method is described by {{citeref|Rushdi|1985|Rushdi|style=plain}}.)</ref>

<ref name="Fletcher_1979">{{cite book |title=An Engineering Approach to Digital Design |author-first=William "Bill" Isaac |author-last=Fletcher<!-- 1938-03-11 – 2020-10-07 https://web.archive.org/web/20210331183318/https://www.legacy.com/us/obituaries/hjnews/name/william-fletcher-obituary?pid=196915249 --> |date=1980 |orig-date=1979 |edition=1 |isbn=0-13-277699-5 |id={{ISBN|978-0-13-2776998}} |publisher=[[Prentice Hall, Inc.]] |publication-place=Englewood-Cliffs, New Jersey, USA |___location=Logan, Utah, USA |lccn=78-27177 |s2cid=38105765 |pages=157–166}} (xviii+766 pages) (NB. The method described here applies to general switching functions that can be incompletely specified with respect to both the map and the entered variables but is limited to cases where only a single variable or single-literal products involving few infrequently-used variables are entered into the map. It is covered as a special case in {{citeref|Rushdi|1987|Rushdi 1987|style=plain}}.)</ref>

<ref name="Mano-Ciletti">{{cite book |title=Digital Design |author-first1=M. Morris<!-- R.? --> |author-last1=Mano |author-first2=Michael D. |author-last2=Ciletti |date= |edition= |isbn= |pages=112–119}}</ref>

<ref name="Rushdi_1983">{{cite journal |title=Symbolic Reliability Analysis with the Aid of Variable-Entered Karnaugh Maps |author-last=Rushdi |author-first=Ali Muhammad Ali |___location=King Abdul Aziz University, Jeddah, Saudi Arabia |date=July 1983<!-- some sources state June 1983 --> |orig-date=1983-01-14, 1982-04-16 |id=Manuscript TR82-38 |journal=[[:d:Q15764762|IEEE Transactions on Reliability]] |issn=0018-9529 |eissn=1558-1721 |publisher=[[IEEE]] |volume=R-32 |number=2 |doi=10.1109/TR.1983.5221510 |pages=134–139 |url=https://www.researchgate.net/publication/224583648_Symbolic_Reliability_Analysis_with_the_Aid_of_Variable-Entered_Karnaugh_Maps |access-date=2021-02-14 |url-status=live |archive-url=https://web.archive.org/web/20210214220829/https://www.researchgate.net/publication/224583648_Symbolic_Reliability_Analysis_with_the_Aid_of_Variable-Entered_Karnaugh_Maps |archive-date=2021-02-14}} [https://web.archive.org/web/20210217022803/https://www.researchgate.net/profile/Ali-Rushdi/publication/224583648_Symbolic_Reliability_Analysis_with_the_Aid_of_Variable-Entered_Karnaugh_Maps/links/0046352c976cfe90ac000000/Symbolic-Reliability-Analysis-with-the-Aid-of-Variable-Entered-Karnaugh-Maps.pdf]</ref>

<ref name="Rushdi_1984">{{cite journal |title=On Reliability Evaluation by Network Decomposition |author-last=Rushdi |author-first=Ali Muhammad Ali |___location=King Abdul Aziz University, Jeddah, Saudi Arabia |journal=[[:d:Q15764762|IEEE Transactions on Reliability]] |issn=0018-9529 |eissn=1558-1721 |publisher=[[IEEE]] |volume=R-33 |number=5 |date=January 1985 |orig-date=December 1984 |doi=10.1109/TR.1984.5221873 |pages=379–384 |url=https://www.researchgate.net/publication/224583780_On_Reliability_Evaluation_by_Network_Decomposition |access-date=2021-02-18 |url-status=live |archive-url=https://web.archive.org/web/20210218194622/https://www.researchgate.net/publication/224583780_On_Reliability_Evaluation_by_Network_Decomposition |archive-date=2021-02-18}} [https://web.archive.org/web/20210218194711/https://www.researchgate.net/profile/Ali-Rushdi/publication/224583780_On_Reliability_Evaluation_by_Network_Decomposition/links/0046352c9778b15282000000/On-Reliability-Evaluation-by-Network-Decomposition.pdf]</ref>

<ref name="Rushdi_1985">{{cite journal |title=Map Derivation of the Minimal Sum of a Switching Function from that of its Complement |author-last=Rushdi |author-first=Ali Muhammad Ali |___location=King Abdul Aziz University, Jeddah, Saudi Arabia |journal=[[:nl:Microelectronics and Reliability|Microelectronics Reliability]] |issn=0026-2714 |date=1985 |volume=25 |issue=6 |doi=10.1016/0026-2714(85)90481-0 |s2cid=120166912 |pages=1055–1065 |url=https://www.academia.edu/27046122/Map_derivation_of_the_minimal_sum_of_a_switching_function_from_that_of_its_complement |access-date=2021-02-17 |url-status=live |archive-url=https://web.archive.org/web/20210217022928/https://www.academia.edu/27046122/Map_derivation_of_the_minimal_sum_of_a_switching_function_from_that_of_its_complement |archive-date=2021-02-17}} (NB. This method is an extension of the method described in {{citeref|Muroga|1979|Muroga|style=plain}} allowing general subsumption and consensus relations among the entered products, but does not handle incompletely specified functions with respect to entered variables. It was further improved in {{citeref|Rushdi|1987|1987|style=plain}}.)</ref>

<ref name="Rushdi_1986">{{cite journal |title=Map Differentiation of Switching Functions |author-last=Rushdi |author-first=Ali Muhammad Ali |___location=King Abdul Aziz University, Jeddah, Saudi Arabia |journal=[[:nl:Microelectronics and Reliability|Microelectronics Reliability]] |issn=0026-2714 |date=1986 |orig-date=1986-04-08 |volume=26 |number=5 |doi=10.1016/0026-2714(86)90233-7 |s2cid= |pages=891–907 |url=https://www.academia.edu/27046126/Map_differentiation_of_switching_functions |access-date=2021-02-18 }}</ref>

<ref name="Rushdi_1987">{{cite journal |title=Improved Variable-Entered Karnaugh Map Procedures |author-last=Rushdi |author-first=Ali Muhammad Ali |___location=King Abdul Aziz University, Jeddah, Saudi Arabia |date=December 1987 |orig-date=1986-06-01 |journal=Computers & Electrical Engineering |issn=0045-7906 |oclc=38840818 |publisher=[[Pergamon Journals Ltd.]] |volume=13 |number=1 |doi=10.1016/0045-7906(87)90021-8 |pages=41–52 |url=https://www.researchgate.net/publication/235924599_Improved_variable-entered_Karnaugh_map_procedures |access-date=2021-02-15 |url-status=live |archive-url=https://web.archive.org/web/20210217023321/https://www.researchgate.net/publication/235924599_Improved_variable-entered_Karnaugh_map_procedures |archive-date=2021-02-17}} [https://web.archive.org/web/20210215213441/https://www.researchgate.net/profile/Ali-Rushdi/publication/235924599_Improved_variable-entered_Karnaugh_map_procedures/links/5b1ae2ae0f7e9b68b429e13d/Improved-variable-entered-Karnaugh-map-procedures.pdf] (NB. An improved variant of the method described in {{citeref|Rushdi|1985|1985|style=plain}}, it covers {{citeref|Fletcher|1980|Fletcher's method|style=plain}} as a special case.)</ref>

<ref name="Green_1986_1">{{cite book |title=Modern Logic Design |author-first=David H. |author-last=Green |edition=1st illustrated |publisher=[[Addison-Wesley Publishing Company, Inc.]] |___location=Wokingham, UK |series=Electronic Systems Engineering Series |date=1986 |isbn=0-201-14541-3 |id={{ISBN|978-0-201-145410}} |lccn=85-20063 |url=https://books.google.com/books/about/Modern_Logic_Design.html?id=Gv0iAAAAMAAJ}} (x<!-- but pages i and ii do not actually exist -->+269+1 pages)</ref>

<ref name="Green_1986_2">{{cite journal |title=Simplification of switching functions using variable-entered maps |author-first=David H. |author-last=Green |journal=[[International Journal of Electronics]] |publisher=[[Taylor & Francis]] |series=Circuit techniques and analysis |volume=75 |issue=5 |date=1993-06-21 |orig-date=1993-05-19 |doi=10.1080/00207219308907166 |pages=877–886 |url=https://www.tandfonline.com/doi/abs/10.1080/00207219308907166 |access-date=2021-02-18}}</ref>

<ref name="Koo_1990">{{cite journal |title=D/Boolean Application in Reliability Analysis |author-first=David Y. |author-last=Koo |date=1990 |journal=Annual Proceedings on Reliability and Maintainability Symposium |orig-date=1990-01-23/25 |doi=10.1109/ARMS.1990.67972 |s2cid=123353547 |pages=295–302 |url=https://ieeexplore.ieee.org/document/67972 |access-date=2021-02-18}}</ref>

<ref name="Misra_1992">{{cite book |title=Reliability Analysis and Prediction: A Methodology Oriented Treatment |chapter=2.2.12 Variable entered Karnaugh's Map |author-first=Krishna B. |author-last=Misra |series=Fundamental Studies in Engineering |publisher=[[Elsevier Science Ltd]] |date=1992-06-01 |isbn=0-44489606-6 |id={{ISBN|978-0-44489606-3}} |pages=56–62 |url=https://books.google.com/books?id=5R26exnr5x4C |chapter-url=https://books.google.com/books?id=5R26exnr5x4C&pg=PA56 |access-date=2021-02-18}} (906 pages)</ref>

<ref name="Malhotra_2019">{{cite web |title=Variable Entrant Map (VEM) in Digital Logic |author-last=Malhotra |author-first=Mohit |date=2019-11-25 |work=Geeks for Geeks |url=https://www.geeksforgeeks.org/variable-entrant-map-vem-in-digital-logic/ |access-date=2021-02-14 |url-status=live |archive-url=https://web.archive.org/web/20210214202528/https://www.geeksforgeeks.org/variable-entrant-map-vem-in-digital-logic/ |archive-date=2021-02-14}}</ref>

<ref name="Permar-Verma_2004">{{cite journal |title=A Novel Method for Minimization of Boolean Functions using Gray Code and development of a Parallel Algorithm |author-first1=Shrish |author-last1=Verma |author-first2=Kiran D. |author-last2=Permar |___location=Government Engineering College, Raipur, India |journal=6th International Workshop on Boolean Problems, 2004-09-23/24 |publication-place=Freiberg, Germany |url=http://www.informatik.tu-freiberg.de/prof2/ws_bp6/slides/Verma_S.pdf |access-date=2021-01-31 |url-status=live |archive-url=https://web.archive.org/web/20071108025839/http://www.informatik.tu-freiberg.de/prof2/ws_bp6/slides/Verma_S.pdf |archive-date=2007-11-08}} [https://www.researchgate.net/publication/242390104_A_Novel_Method_for_Minimization_of_Boolean_Functions_using_Gray_Code_and_development_of_a_Parallel_Algorithm] (24 pages)</ref>

<ref name="Verma_2007">{{cite book |title=Paraboomig: A Novel Method for Minimization of Boolean Functions using Gray Code & Its Parallel Algorithm |author-first=Shrish |author-last=Verma |editor-first=Kiran D. |editor-last=Permar |type=thesis |hdl=10603/30623 |___location=National Institute of Technology, Raipur, India |url=https://shodhganga.inflibnet.ac.in/handle/10603/30623?mode=full |access-date=2021-01-31 |url-status=live |archive-url=https://web.archive.org/web/20210131194804/https://shodhganga.inflibnet.ac.in/handle/10603/30623?mode=full |archive-date=2021-01-31}} [https://web.archive.org/web/20210131194654/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/1/01_title.pdf][https://web.archive.org/web/20210131195137/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/2/02_declaration.pdf][https://web.archive.org/web/20210131195416/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/3/03_certificate.pdf][https://web.archive.org/web/20210131195603/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/4/04_certificate.pdf][https://web.archive.org/web/20210131195651/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/5/05_acknowledgement.pdf][https://web.archive.org/web/20210131194725/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/6/06_content.pdf][https://web.archive.org/web/20210214175857/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/7/07_chapter%201.pdf][https://web.archive.org/web/20170110113704/http://shodhganga.inflibnet.ac.in/bitstream/10603/30623/8/08_chapter%202.pdf][https://web.archive.org/web/20210214180001/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/9/09_chapter%203.pdf][https://web.archive.org/web/20210214180037/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/10/10_chapter%204.pdf][https://web.archive.org/web/20210214180104/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/11/11_chapter%205.pdf][https://web.archive.org/web/20161104170733/http://shodhganga.inflibnet.ac.in/bitstream/10603/30623/12/12_chapter%206.pdf][https://web.archive.org/web/20210214180503/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/13/13_chapter%207.pdf][https://web.archive.org/web/20210131195742/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/14/14_references.pdf][https://web.archive.org/web/20210131195815/https://shodhganga.inflibnet.ac.in:8443/jspui/pdfToThesis.jsp?toHandle=https://shodhganga.inflibnet.ac.in/handle/10603/30623&toFile=https://shodhganga.inflibnet.ac.in/bitstream/10603/30623/15/15_appendix.pdf]</ref>

<ref name="Alharbi_2020_1">{{cite book |chapter=Truth Graph: A Novel Method for Minimizing Boolean Algebra Expressions by Using Graphs |author-first=Eisa |author-last=Alharbi |title=Diagrammatic Representation and Inference |editor-first1=Ahti-Veikko |editor-last1=Pietarinen |editor-first2=Peter |editor-last2=Chapman |editor-first3=Leonie |editor-last3=Bosveld-de Smet |editor-first4=Valeria |editor-last4=Giardino |editor-first5=James |editor-last5=Corter |editor-first6=Sven |editor-last6=Linker |isbn=978-3-030-54248-1 |journal=Proceedings of the 11th International Conference on Theory and Application of Diagrams "Diagrams 2020", Tallinn, Estonia, 2020-08-24/28 |___location=Ahmadi, Kuwait |doi=10.1007/978-3-030-54249-8_36 |series=[[Lecture Notes in Computer Science]] (LNCS) / [[Lecture Notes in Artificial Intelligence]] (LNAI) |publisher=[[Springer Science+Business Media]] |volume=12169 |type=conference paper |date=2020-08-17 |pages=461–469 |url=https://www.researchgate.net/publication/343688223_Truth_Graph_A_Novel_Method_for_Minimizing_Boolean_Algebra_Expressions_by_Using_Graphs |chapter-url=https://link.springer.com/content/pdf/10.1007%2F978-3-030-54249-8_36.pdf |access-date=2020-11-08 |url-status=live |archive-url=https://web.archive.org/web/20201108140209/https://link.springer.com/content/pdf/10.1007%2F978-3-030-54249-8_36.pdf |archive-date=2020-11-08}} [https://link.springer.com/chapter/10.1007/978-3-030-54249-8_36] (9 pages)</ref>

<ref name="Alharbi_2020_2">{{cite video |title=Truth Graph expressions - Truth Graph Minimization Method |author-first=Eisa |author-last=Alharbi |type=video |date=2020-08-24 |orig-date=2020-06-15 |url=https://www.youtube.com/watch?v=l6xNfMis890 |archive-url=https://ghostarchive.org/varchive/youtube/20211219/l6xNfMis890 |archive-date=2021-12-19 |url-status=live|access-date=2021-02-14}}{{cbignore}}</ref>

<ref name="Vingron_2003">{{cite book |author-last=Vingron |author-first=Shimon Peter |title=Switching Theory: Insight Through Predicate Logic |orig-date=2003-11-05 |publisher=[[Springer-Verlag]] |___location=Berlin, Heidelberg, New York |isbn=3-540-40343-4 |edition=1 |pages=207–217 |chapter=Chapter 20. Reduced Karnaugh Maps |date=2004 |doi=10.1007/978-3-662-10174-2 |url=https://books.google.com/books?id=pzoqZj7uAHwC&pg=PA207}}</ref>

<ref name="Vingron_2012">{{cite book |author-last=Vingron |author-first=Shimon Peter |title=Logic Circuit Design: Selected Methods |chapter=5.5 Karnaugh Trees and Map-Entered Variables |publisher=[[Springer-Verlag]] |publication-place=Berlin & Heidelberg, Germany |___location=Hinterbrühl, Austria |isbn=978-3-642-43256-9 |edition=1 |pages=63–66 |date=2012 |doi=10.1007/978-3-642-27657-6}} (xiv+258 pages)</ref>

<ref name="Kartalopoulos_1982">{{cite journal |title=The minimization of logic functions utilizing two-dimensional representations of hypercubes |author-first=Stamatios V. |author-last=Kartalopoulos |date=1982-02-18 |orig-date=1982-01-28 |journal=[[International Journal of Electronics]] |publisher=[[Taylor & Francis]] |volume=53 |issue=3 |doi=10.1080/00207218208901505 |pages=233–245 |url=https://www.tandfonline.com/doi/abs/10.1080/00207218208901505 |access-date=2021-01-31}}</ref>

<ref name="McCalla_1990">{{cite conference |title=A Minterm-Ring Algorithm for Simplifying Boolean Expressions |author-first=Thomas Richard |author-last=McCalla |book-title=Proceedings of the 33rd Midwest Symposium on Circuits and Systems (MWSCAS): August 12-15, 1990, Calgary Convention Centre, Calgary, Alberta, Canada<!-- Volume 2 --> |editor-first1=Ronald H. |editor-last1=Johnston |editor-first2=Behrooz |editor-last2=Nowrouzian |editor-first3=Laurence E. |editor-last3=Turner |date=1991 |orig-date=1990-08-12/14 |publisher=[[IEEE]] / Department of Electrical Engineering, University of Calgary & University of Alberta |___location=Calgary Convention Centre, Calgary, Alberta, Canada |volume=II |isbn=0-7803-0081-5 |doi=10.1109/MWSCAS.1990.140924 |id=Cat. No. 90CH2819-1 |pages=1127-1130 |url=https://ieeexplore.ieee.org/document/140924/similar#similar |access-date=2021-02-15}} [https://books.google.com/books?id=EQxWAAAAMAAJ&q=%22minterm-ring+algorithm%22&dq=%22minterm-ring+algorithm%22]</ref>

<ref name="McCalla_1992">{{cite book |title=Digital Logic and Computer Design |chapter=3.5 Minterm-Ring Maps and Karnaugh Maps in 5 and 6 variables |author-last=McCalla |author-first=Thomas Richard |___location=University of Science & Arts of Oklahoma, Chickasha, Oklahoma, USA |publisher=[[Macmillan Publishing]] |publication-place=Englewood Cliffs, New Jersey, USA |date=1992 |edition=1 |series=Merrill's International Series in Engineering Technology |isbn=0-675-21170-0 |id={{ISBN|978-0-675-21170-3}} |lccn=91-17012 |pages=119-135, 201-203 [119, 122, 123, 125-128, 130-132, 135] |url=https://books.google.com/books?id=LWFTAAAAMAAJ&q=%22minterm-ring+algorithm%22&dq=%22minterm-ring+algorithm |access-date=2021-02-20}} (xx+790+6 pages)</ref>

<ref name="Morelli-Reynaga_2004">{{cite book |author-first=Jorge Alberto |author-last=Morelli Reynaga |title=Métodos Gráficos Alternos para Simplificación de Funciones Booleanas de 5 y 6 Variables |language=es |type=Thesis |publisher=[[Instituto Tecnológico de Sonora]] (ITSON) |___location=Sonora, Mexico |date=January 2004}}</ref>

<ref name="Romero-Aguirre-Murrieta-Lee_2005">{{cite journal |title=A Survey of the Graphic Alternate Method for Boolean Functions Simplification |author-first1=Eduardo |author-last1=Romero-Aguirre |author-first2=Juan Carlos |author-last2=Murrieta-Lee |date=2005-03-02 |orig-date=2005-02-28 |series=Education |journal=Proceedings of the 15th International Conference on Electronics, Communications and Computers (CONIELECOMP 2005) |publisher=[[IEEE Computer Society]] |volume=1 |isbn=0-7695-2283-1 |doi=10.1109/CONIEL.2005.12 |___location=[[Instituto Tecnológico de Sonora]] (ITSON), Puebla, Mexico |pages=328-334 |url=https://www.researchgate.net/publication/4162402_A_Survey_of_the_Graphic_Alternate_Method_for_Boolean_Functions_Simplification |access-date=2021-02-17 |url-status=live |archive-url=https://web.archive.org/web/20210215195906/https://www.researchgate.net/publication/4162402_A_Survey_of_the_Graphic_Alternate_Method_for_Boolean_Functions_Simplification |archive-date=2021-02-15}} [https://web.archive.org/web/20210217022231/https://www.researchgate.net/profile/Eduardo_Romero11/publication/4162402_A_Survey_of_the_Graphic_Alternate_Method_for_Boolean_Functions_Simplification/links/553916020cf2239f4e7c5149/A-Survey-of-the-Graphic-Alternate-Method-for-Boolean-Functions-Simplification.pdf][https://ieeexplore.ieee.org/document/1488582][https://www.computer.org/csdl/proceedings-article/conielecomp/2005/22830328/12OmNynsbuS]</ref>

<ref name="Peticolas-Mahoney_1963">{{cite book |title=Computer circuits and computer systems |author-first1=Alfred B. |author-last1=Peticolas |author-first2=Matthew V. |author-last2=Mahoney |id=C-15. A674036 |publisher=[[RCA Institutes, Inc.]] |publication-place=New York, USA |type=Laboratory manual |date=1963-12-20 |url=https://books.google.com/books?id=jh0hAQAAIAAJ&pg=PA712}} (NB. This work formed the basis for the {{citeref|Peticolas|Mahoney|1964|1964 course manual|style=plain}}.)</ref>

<ref name="Peticolas-Mahoney_1964">{{cite book |title=Logical Design for Digital Systems |id=A715535. N65-25354 |publisher=[[RCA Institutes, Inc.]] |publication-place=New York, USA |author-first1=Alfred B. |author-last1=Peticolas |author-first2=Matthew V. |author-last2=Mahoney |date=1964-08-10 |url=https://books.google.com/books?id=M0k0i6yyMzUC&pg=RA2-PA12}} [https://books.google.com/books?id=3IjMUTEQ7qEC&pg=PA2334][https://books.google.com/books?id=_x0hAQAAIAAJ&pg=PA1968] (191+1 pages) (NB. This course manual is based on the {{citeref|Peticolas|Mahoney|1963|1963 laboratory manual|style=plain}}.)</ref>

<ref name="Peticolas-Mahoney-Laguzzi_1967">{{cite book |title=Logic Design |type=lecture notes |id=A917290 |publisher=[[RCA Institutes, Inc.]] |publication-place=New York, USA |editor-first1=Alfred B. |editor-last1=Peticolas |editor-first2=Matthew V. |editor-last2=Mahoney |editor-first3=Mario C. |editor-last3=Laguzzi |date=1967-05-08 |orig-date=1966 |edition=4 |url=https://books.google.com/books?id=SCghAQAAIAAJ&pg=PA837}} (185 pages) (NB. This fourth edition of a course student binder, based on the {{citeref|Peticolas|Mahoney|1964|earlier manual|style=plain}}, is mentioned in a [[#RCA-1968|1968 RCA flyer]].)</ref>

<ref name="RCA_1966">{{cite book |title=Logic Design |date=1966-07-22 |author=School of Custom Educational Program |publisher=[[RCA Institutes, Inc.]] |publication-place=New York, USA |type=flyer |id=CE-105-R56. ark:/13960/t56f22q9v |url=https://archive.org/details/TNM_Logic_Design_and_Digital_Electronics_seminars_20170915_0029 |access-date=2021-02-20 |quote=[…] Staff […] Bradford Daggett, Director […] Matthew V. Mahoney, Admin., Development […] Alfred B. Peticolas, Dean […] Mario C. Laguzzi, Member of Technical Staff […] Edward K. Marrie, Member of Technical Staff […] Abraham Schwartz, Member of Technical Staff […]}} [https://archive.org/details/TNM_Logic_Design_and_Digital_Electronics_seminars_20170915_0029]</ref>

<ref name="RCA_1968">{{cite book |ref=RCA-1968 |title=A Syllabus on the Content of Logic Design: A Five-day Educational Seminar For Engineers Presented by RCA Institutes |chapter=Logic Design: Development of the Mahoney Map |date=1968-11-25 |publisher=[[RCA Institutes, Inc.]] |___location=Syracuse, New York, USA |publication-place=New York, USA |type=flyer |id=ark:/13960/t8kd8cx8z |url=https://archive.org/details/TNM_Computer_logic_design_seminar_1968_-_RCA_20180128_0177 |access-date=2021-02-20 |quote=[…] The Planning Board […] This seminar has been developed through extensive field research by the Institute for Professional Development in consultation with RCA Institutes' Board of Technical Advisers, representing various technical research and educational activities of RCA and its subsidiaries. […] B. I. Daggett (Director), J. H. Sneddon (Manager, Administration), D. B. Kenney (Industrial Sales), B. V. Ferguson (Direct Marketing), M. V. Mahoney (Research & Development), A. B. Peticolas (Administrator), J. B. Wetterau (Group Leader), E. Fleisher (Staff Member), M. C. Laguzzi (Staff Member), R. D. Lindskog (Staff Member), C. L. Pearce (Staff Member), P. Pennisi (Staff Member), C. H. Saville (Staff Member), R. E. Weiss (Staff Member) […] Table of Contents […] The Matrix Approach to Logic Designation Number Notation […] Designation Numbers of Boolean Elements and Functions, Logical Operations with Designation Numbers […] The Logic Map […] Development of the Mahoney Map […]}} [https://archive.org/details/TNM_Computer_logic_design_seminar_1968_-_RCA_20180128_0177] (NB. This 1968 flyer mentions Mahoney as RCA R&D member. A 184 pages {{citeref|Peticolas|Mahoney|Laguzzi|1967|lecture notes|style=plain}} binder was available to course members.)</ref>

<ref name="RCA_1970">{{cite book |title=RCA - A Course in Logic Design - A unique learning experience for those who solve digital circuit design problems, or who evaluate Logic Design effectiveness - A seminar prepared by the Institute for Professional Development of RCA Institutes |chapter=Logic Design: Development of the Mahoney Map |date=1970-08-24 |publisher=[[RCA Institutes, Inc.]] |___location=Montreal, Quebec, Canada |publication-place=Clark, New Jersey, USA |type=flyer |work=Lecture Notes Manual (student binder) |id=ark:/13960/t7jq7zk56 |page=2.5 |url=https://archive.org/details/TNM_Logic_design_course_-_RCA_1970_20180329_0077 |access-date=2021-02-16 |quote-page=2.5 |quote=[…] RCA courses for Professional Development, since our programs were first formed in 1964. […] Logic Design […] The reduction technique to be explored below and used henceforth in our logic design work is a variation on the [[Veitch diagram]]. This modification, introduced by M.&nbsp;V. Mahoney, is designed to work directly from designation numbers; the designer need never see a Boolean expression other than the final, simplified form. With this particular map, the position of each [[minterm]] is invariant, regardless of the number of variables, so that the map pattern is easily memorized. […] Definitions and Basic Concepts […] Let f&nbsp;= any function […] #f&nbsp;= the designation number of f (read "designation f") […] n&nbsp;= number of variables (f is a function of n variables) […] p&nbsp;= number of positions in #f […] p&nbsp;= number of square subsets in universe […] i&nbsp;= position identification […] m_i&nbsp;= the minterm occupying position i […] We will first assume that n&nbsp;= 0. As with the original [[Venn diagram]], the universe will be a rectangle. With n&nbsp;= 0, we cannot subdivide this universal set. There is no need to, however, for if n&nbsp;= 0, p&nbsp;= 2⁰&nbsp;= 1. In other words, there is only one position in #f, the ''zero'' position, and only one possible minterm, m₀. The rectangular universe will represent m₀ and will be marked with the minterm subscript: […] n&nbsp;= 0 ''[o]'' No. of subsets (squares)&nbsp;= no. of minterm positions&nbsp;= p&nbsp;= 2ⁿ&nbsp;= 2⁰&nbsp;= 1 […] Although there are no variables, there are still 2^p&nbsp;= 2 functions possible. These functions must be the two constants, 1 and 0. […] If f&nbsp;= 0, then #f&nbsp;= 0; i.e. m₀ is ''empty''. This is indicated by leaving the diagram unmarked: ''[o]'' #f&nbsp;= 0; f&nbsp;= 0; p&nbsp;= 2ⁿ&nbsp;= 1 […] If f&nbsp;= 1, then #f&nbsp;= 1; i.e. the m₀ position is occupied. This is indicated with a diagonal mark: ''[/o/]'' #f&nbsp;= 1; f&nbsp;= 1; f&nbsp;= m₀ […] The above map would, of course, never be needed in a practical problem. Here it is used only as an introduction, for the orderly evolution of the general n-variable map. […] Map Development […] Visualize the map as a large sheet marked with a checkerboard pattern of squares. Now fold the lower half upwards so it is hidden ''behind'' the top. Fold the right hand half behind the left. Repeat the above procedures alternately, until only the single upper left square remains visible. This square is the set representing minterm zero, the square used as our starting point. […]}} [https://archive.org/details/TNM_Logic_design_course_-_RCA_1970_20180329_0077] (NB. This 1970 flyer mentions that the course was established in 1964.)</ref>

<ref name="Fezer_1970">{{cite journal |title=The evolution and development of RCA Institutes |author-first=Harold |author-last=Fezer<!-- |section=Institute for Professional Development --> |journal=[[RCA Engineer]] |volume=16 |number=4 |date=December 1970 – January 1971 |publisher=[[RCA Corporate Engineering Services]] / [[RCA Corporation]] |publication-place=New Jersey, USA |page=64–69 [67] |url=https://worldradiohistory.com/ARCHIVE-RCA/RCA-Engineer/1970-12-01.pdf |access-date=2021-02-19 |url-status=live |archive-url=https://web.archive.org/web/20210219114652/https://worldradiohistory.com/ARCHIVE-RCA/RCA-Engineer/1970-12-01.pdf |archive-date=2021-02-19 |quote-page=67 |quote=Logic design (5 days) - provides the numerical and matrix tools required to select the most straightforward, practical approach to digital circuit design. The Mahoney Map and designation numbers are thoroughly covered.}} [https://books.google.com/books?id=4jRWAAAAMAAJ&q=%22Mahoney+map%22&dq=%22Mahoney+map%22]</ref>

<ref name="Moser_1973">{{cite magazine |title=Checking wired-AND gates in just one test setup |author-first=Carl Woodrow |author-last=Moser, Jr. |magazine=[[Electronics (magazine)|Electronics]] - The International Magazine of Electronics Technology |issn=0013-5070 |volume=46 |number=15 |department=Engineer's notebook |publisher=[[McGraw-Hill, Inc.]] |publication-place=New York, USA |date=1973-07-19 |orig-date=January 1973 |___location=Western Electric, Winston-Salem, North Carolina, USA |page=127 |url=https://www.researchgate.net/publication/294310378_CHECKING_WIRED-AND_GATES_IN_JUST_ONE_TEST_SETUP |access-date=2021-02-16 |url-status=live |archive-url=https://web.archive.org/web/20210216180105/https://www.researchgate.net/publication/294310378_CHECKING_WIRED-AND_GATES_IN_JUST_ONE_TEST_SETUP |archive-date=2021-02-16 |quote-page=127 |quote=[…] One of the most difficult types of circuits to test effectively is an array of wired-AND logic gates. But a standard design aid, the Mahoney map, can be used to determine the best waveform setup for completely testing such an array. The Mahoney map is identical to the [[Karnaugh map]], with the exception of the [[minterm]] digits. […]}} [<!-- https://worldradiohistory.com/Archive-Electronics/70s/73/Electronics-1973-07-19.pdf -->https://web.archive.org/web/20210219113036/https://worldradiohistory.com/Archive-Electronics/70s/73/Electronics-1973-07-19.pdf][https://books.google.com/books?id=FlVJAQAAIAAJ&q=%22Mahoney+map%22&dq=%22Mahoney+map%22] (1 page)</ref>

<ref name="Holten_1974">{{cite magazine |title=Double multiplexer logic capability - by using one of the input variables to drive some data lines. A modified Karnaugh map helps you choose the right ones. |magazine=[[Electronic Design (magazine)|Electronic Design]] - For Engineers and Engineering Managers |issn=0013-4872 |author-first=Cornelis "Cornelius"<!-- has also published under this name --> |author-last=van Holten |___location=Delft Technical University, Delft, Netherlands |volume=22 |number=17 |date=August 1974 |publisher=[[Hayden Publishing Company, Inc.]] |publication-place=Rochelle Park, New Jersey, USA |pages=86–89 [87, 89] |url=https://books.google.com/books?id=ydwEAQAAIAAJ&dq=%22Mahoney+map%22&focus=searchwithinvolume&q=Mahoney |access-date=2021-02-20 }} (4 pages)</ref>

<ref name="Krehbiel_1996">{{cite book |author-last=Krehbiel |author-first=Paul |editor-first=David |editor-last=Bonal |title=(Private communication) |date=1996-12-05}} (NB. Cited in {{citeref|Bonal|2013|Bonal|style=plain}}.[https://web.archive.org/web/20210216181044/http://davidbonal.com/karnaugh-and-mahoney-map-methods-for-minimizing-boolean-expressions/])</ref>

<ref name="Mann_2005">{{cite web |title=Karnaugh Maps Tutorial |author-first=Kenneth |author-last=Mann |work=PhysicsForums |date=2005-12-18 |orig-date=2005-11-19 |url=https://www.physicsforums.com/threads/karnaugh-maps-tutorial.100628/

|access-date=2021-02-16 |url-status=live |archive-url=https://web.archive.org/web/20210216193735/https://www.physicsforums.com/threads/karnaugh-maps-tutorial.100628/

|archive-date=2021-02-16 |quote=[…] about a decade after {{citeref|Karnaugh|1953|Karnaugh's paper|style=plain}}, an individual named Matthew Mahoney observed a symmetrical reflecting approach behind the process of map construction which showed that maps could be extended in design beyond four variables, and from that approach he came up with a slightly different design which, was termed the 'Mahoney Map'. […] In the early 1960s, Matthew Mahoney more precisely defined the basic mechanism through which the logic-map operates. Using this principle (which we have already laid out) he defined and laid out what came to be called the "Mahoney-Map". Essentially, the Mahoney Map is a variation of the [[Karnaugh Map]], and the principles will apply equally in both cases. […]}} [<!-- https://www.physicsforums.com/threads/karnaugh-maps-tutorial.100628/page-2-->https://web.archive.org/web/20190227063103/https://www.physicsforums.com/threads/karnaugh-maps-tutorial.100628/page-2][<!-- https://www.physicsforums.com/threads/karnaugh-maps-tutorial.100628/page-3 -->https://web.archive.org/web/20190227063041/https://www.physicsforums.com/threads/karnaugh-maps-tutorial.100628/page-3]</ref>

<ref name="Goth_2009">{{cite web |title=Mahoney Map - An alternative to Karnaugh Maps |author-first=Andrew "Andy" Michael |author-last=Goth |___location=Midlothian, Texas, USA |date=2012-11-27 |orig-date=2009-01-28 |url=https://wiki.tcl-lang.org/page/Mahoney+Map |access-date=2021-02-16 |url-status=live |archive-url=https://web.archive.org/web/20210216163028/https://wiki.tcl-lang.org/page/Mahoney+Map |archive-date=2021-02-16}}</ref>

<ref name="Bonal_2013">{{cite web |title=Karnaugh and Mahoney: Map Methods for Minimizing Boolean Expressions |at=Section 3. Mahoney Maps: Implementing the Sign of Zoro |author-first=David |author-last=Bonal |date=2013-10-19 |url=http://davidbonal.com/karnaugh-and-mahoney-map-methods-for-minimizing-boolean-expressions/ |access-date=2021-02-16 |url-status=live |archive-url=https://web.archive.org/web/20210216181044/http://davidbonal.com/karnaugh-and-mahoney-map-methods-for-minimizing-boolean-expressions/ |archive-date=2021-02-16}}</ref>

}}

== Further reading ==

* {{cite book |author-last1=Lind |author-first1=Larry Frederick |author-last2=Nelson |author-first2=John Christopher Cunliffe |title=Analysis and Design of Sequential Digital Systems |date=1977 |publisher=[[Macmillan Press]] |isbn=0-33319266-4 |url=https://archive.org/details/AnalysisDesignOfSequentialDigitalSystems/}} (146 pages)

* {{cite journal |author-last=Hwa |author-first="Sherman" Hsuen Ren |title=A Method of Generating Prime Implicants of a Boolean Expression |journal=[[IEEE Transactions on Computers]] |issn=0018-9340 |eissn=1557-9956 |id=CD-{{ISSN|2326-3814}}. 1F09 |publisher=[[IEEE]] |volume=C-23 |issue=6 |date=June 1974 |doi=10.1109/T-C.1974.224003 |s2cid=10646917 |pages=637–641 |url=https://ieeexplore.ieee.org/document/1672596 |access-date=2020-05-12 |postscript=;}} {{cite book |author-last=Hwa |author-first="Sherman" Hsuen Ren |title=A Method of Generating Prime Implicants of a Boolean Expression |publisher=Basser Department of Computer Science, [[University of Sydney]] |date=April 1973 |id=Technical Report 82}}

* {{cite book |author-last1=Lind |author-first1=Larry Frederick |author-last2=Nelson |author-first2=John Christopher Cunliffe |title=Analysis and Design of Sequential Digital Systems |date=1977 |publisher=[[Macmillan Press]] |isbn=0-33319266-4 |url=https://archive.org/details/AnalysisDesignOfSequentialDigitalSystems/}} [https://books.google.com/books?id=fj1dDwAAQBAJ] (146 pages)

* {{cite journal |title=A method of generating prime factors of a Boolean Expression in a conjunctive normal form with the possibility of inclusion of Don't care combination |author-first=Debidas |author-last=Ghosh |journal=Journal of Technology |volume=XXII |number=1 |date=June 1977 |orig-date=1977-01-21 |___location=Department of Mathematics, Bengal Engineering College, Howrah, India |url=https://shodhganga.inflibnet.ac.in/bitstream/10603/158814/10/10_reprints.pdf |access-date=2020-05-12 |url-status=live |archive-url=https://web.archive.org/web/20200512132724/https://shodhganga.inflibnet.ac.in/bitstream/10603/158814/10/10_reprints.pdf |archive-date=2020-05-12}}

* {{cite book |title=Synthesis and Optimization of Digital Circuits |author-first=Giovanni |author-last=De Micheli |author-link=Giovanni De Micheli |date=1994 |publisher=[[McGraw-Hill]] |isbn=0-07-016333-2}} (NB. Chapters 7–9 cover combinatorial two-level, combinatorial multi-level, and respectively sequential circuit optimization.)

* {{cite book |author-first1=Gary D. |author-last1=Hachtel |author-first2=Fabio |author-last2=Somenzi |title=Logic Synthesis and Verification Algorithms |date=2006 |orig-date=1996 |publisher=[[Springer Science & Business Media]] |isbn=978-0-387-31005-3}}

* {{cite book |author-first1=Zvi |author-last1=Kohavi |author-first2=Niraj K. |author-last2=Jha |title=Switching and Finite Automata Theory |edition=3rd |publisher=[[Cambridge University Press]] |date=2009 |isbn=978-0-521-85748-2 |chapter=4–6}}

* {{cite book |title=The Art of Computer Programming |title-link=The Art of Computer Programming |date=2010 |author-last=Knuth |author-first=Donald Ervin |author-link=Donald Ervin Knuth |volume=4A |chapter=7.1.2: Boolean Evaluation |publisher=[[Addison-Wesley]] |pages=96–133 |isbn=978-0-201-03804-0}}

* {{cite book |author-first=Rob A. |author-last=Rutenbar |title=Multi-level minimization, Part I: Models & Methods |type=lecture slides |publisher=[[Carnegie Mellon University]] (CMU) |id=Lecture 7 |url=https://www.ece.cmu.edu/~ee760/760docs/lec07.pdf |access-date=2018-01-15 |url-status=live |archive-url=https://web.archive.org/web/20180115125725/https://www.ece.cmu.edu/~ee760/760docs/lec07.pdf |archive-date=2018-01-15 |postscript=;}} {{cite book |author-first=Rob A. |author-last=Rutenbar |title=Multi-level minimization, Part II: Cube/Cokernel Extract |type=lecture slides |publisher=[[Carnegie Mellon University]] (CMU) |id=Lecture 8 |url=https://www.ece.cmu.edu/~ee760/760docs/lec08.pdf |access-date=2018-01-15 |url-status=live |archive-url=https://web.archive.org/web/20180115125733/https://www.ece.cmu.edu/~ee760/760docs/lec08.pdf |archive-date=2018-01-15}}

* {{cite journal |author-last1=Tomaszewski |author-first1=Sebastian P. |author-last2=Celik |author-first2=Ilgaz U. |author-last3=Antoniou |author-first3=George E. |title=WWW-based Boolean function minimization |journal=[[International Journal of Applied Mathematics and Computer Science]] |volume=13 |issue=4 |date=December 2003 |orig-date=2003-03-05, 2002-04-09 |pages=577–584 |url=http://matwbn.icm.edu.pl/ksiazki/amc/amc13/amc13414.pdf |access-date=2020-05-10 |url-status=live |archive-url=https://web.archive.org/web/20200510214937/http://matwbn.icm.edu.pl/ksiazki/amc/amc13/amc13414.pdf |archive-date=2020-05-10}} [https://www.researchgate.net/publication/228862329_WWW-based_Boolean_function_minimization][https://archive.today/20180115131301/http://matwbn.icm.edu.pl/ksiazki/amc/amc13/amc13414.pdf] (7 pages)

* <!-- Kudielka already cited above, but contains other relevant papers as well -->{{cite book |editor-first1=Johannes |editor-last1=Dörr |editor-first2=Ernst Ferdinand |editor-last2=Peschl |editor-link2=Ernst Ferdinand Peschl |editor-first3=Heinz |editor-last3=Unger |editor-link3=:de:Heinz Unger (Mathematiker) |author-first1=Alexander |author-last1=Wilhelmy |author-first2=Viktor |author-last2=Kudielka |author-first3=Peter |author-last3=Deussen |author-first4=Karl Heinz |author-last4=Böhling |author-link4=:de:Karl Heinz Böhling |author-first5=Wolfgang |author-last5=Händler |author-link5=Wolfgang Händler |author-first6=Joachim |author-last6=Neander |title=2. Colloquium über Schaltkreis- und Schaltwerk-Theorie - Vortragsauszüge vom 18. bis 20. Oktober 1961 in Saarbrücken |language=de |series=Internationale Schriftenreihe zur Numerischen Mathematik [International Series of Numerical Mathematics] (ISNM) |volume=4 |date=January 1963 |orig-date=1961-10-18 |edition=2013-12-20 reprint of 1st |___location=Institut für Angewandte Mathematik, [[Universität Saarbrücken]], Rheinisch-Westfälisches Institut für Instrumentelle Mathematik |publisher=[[Springer Basel AG]] / [[Birkhäuser Verlag Basel]] |isbn=978-3-0348-4081-1 |doi=10.1007/978-3-0348-4156-6 |url=https://books.google.com/books?id=exCmBgAAQBAJ |access-date=2020-04-15 }} (152 pages)

* {{cite journal |author-first1=Robert King |author-last1=Brayton |author-link1=:wikidata:Q15842652 |author-first2=Richard L. |author-last2=Rudell |author-first3=Alberto Luigi |author-last3=Sangiovanni-Vincentelli |author-link3=Alberto Luigi Sangiovanni-Vincentelli |author-first4=Albert R. |author-last4=Wang |title=MIS: A Multiple-Level Logic Optimization System |journal=[[IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems]] |volume=6 |number=6 |pages=1062–1081 |date=December 1987 |doi=10.1109/TCAD.1987.1270347 |url=https://www.researchgate.net/publication/3225465_MIS_A_Multiple-Level_Logic_Optimization_System}} (MIS) (20 pages)

* {{cite journal |author-first1=Aart J. |author-last1=De Geus |author-link1=Aart de Geus |author-first2=William W. |author-last2=Cohen |title=A Rule-Based System for Optimizing Combinational Logic |journal=[[IEEE Design & Test of Computers]] |issn=0740-7475 |eissn=1558-1918 |volume=2 |number=4 |date=July–August 1985 |doi=10.1109/MDT.1985.294719 |s2cid=46651690 |pages=22–32 |url=https://dl.acm.org/doi/10.1109/MDT.1985.294719 |access-date=2021-02-19 |url-status=live |archive-url=https://web.archive.org/web/20210219095415/https://dl.acm.org/doi/10.1109/MDT.1985.294719 |archive-date=2021-02-19}} (11 pages) [https://web.archive.org/web/20210219102125/https://www.computer.org/csdl/magazine/dt/1985/04/04069623/13rRUy3gmYS] (SOCRATES)

* {{cite book |title=Advanced Techniques in Logic Synthesis, Optimizations and Applications |editor-first1=Sunil P. |editor-last1=Khatri |editor-first2=Kanupriya |editor-last2=Gulati |edition=1 |isbn=978-1-4419-7517-1 |publisher=[[Springer Science+Business Media, LLC]] |date=2011 |publication-place=New York / Dordrecht / Heidelberg / London}} (xxii+423+1 pages)

* {{cite magazine |title=A More Efficient Use of Karnaugh Maps |author-first=Jobst E. |author-last=Jesse |magazine=Computer Design |issn=0010-4566 |id={{CODEN|CMPDA}} |oclc=828863003 |publisher=Computer Design Publishing Corporation |publication-place=Concord, Massachusetts, USA |___location=Sunnyvale, California, USA |volume=11 |issue=2 |date=February 1972 |pages=80–82 |url=https://books.google.com/books?id=oSFHAQAAIAAJ&dq=editions%3ASTANFORD36105000958269&focus=searchwithinvolume&q=A+More+Efficient+Use+of+Karnaugh+Maps}} (3 pages)

* {{cite journal |author-first=Bernd |author-last=Reusch |title=Generation of Prime Implicants from Subfunctions and a Unifying Approach to the Covering Problem |journal=[[IEEE Transactions on Computers]] |issn=0018-9340 |eissn=1557-9956 |id=CD-{{ISSN|2326-3814}} |publisher=[[IEEE]] |volume=C-24 |number=9 |date=September 1975 |doi=10.1109/T-C.1975.224338 |s2cid=32090834 |pages=924–930 |url=https://dl.acm.org/doi/abs/10.1109/T-C.1975.224338 |access-date=2021-02-19}} (7 pages)

* {{cite magazine |title=To the Editor |department=Letters to the editor |author-first=R. L. |author-last=Dineley |magazine=Computer Design |issn=0010-4566 |id={{CODEN|CMPDA}} |oclc=828863003 |publisher=Computer Design Publishing Corporation |publication-place=Concord, Massachusetts, USA |volume=8 |issue=4 |date=April 1969 |page=16 |url=https://books.google.com/books?id=Uy4-AQAAIAAJ&dq=%22infrequent+variable%22+karnaugh&focus=searchwithinvolume&q=Dineley |quote-page=16 |quote=[…] I would like to offer a method for the simplification of [[maxterm]] type [[Boolean expression]] by use of the [[Veitch diagram]]. To the best of my knowledge, I am the originator of the method, having derived it in 1960 while attending the Digital Computer Fundamentals course at [[Redstone Arsenal]]. Most texts simplify the maxterm ([[product of sums]]) type expression by plotting the individual terms on separate Veitch diagrams and then overlaying the diagrams to discover the intersects, or "anded," function. […] The method offered here permits the plotting of all terms on one diagram with the "anded" relationship easily discernible. […] Each sum term of the expression is assigned a symbol. This symbol is plotted on the Veitch for each of the or'd factors of the term. The "and" function occurs whenever any square or combination of 2ⁿ adjacent squares contain all of the assigned symbols. A simple example will illustrate. […] (A + BC)^[1] (A + C)^[2] = A + BC […] Yours truly, R. L. Dineley, Sperry Rand Corp.}} (1 page) (NB. Referred to in [[#Schultz-1969-2|Schultz's letter]] above.)

* {{cite book |title=A Survey of Literature on Function Decomposition |chapter=6. Historical Overview of the Research on Decomposition |version=Version IV |author-first1=Marek A. |author-last1=Perkowski |author-first2=Stanislaw |author-last2=Grygiel |publisher=Functional Decomposition Group, Department of Electrical Engineering, Portland University, Portland, Oregon, USA |date=1995-11-20 |citeseerx=10.1.1.64.1129 |url=http://web.cecs.pdx.edu/~mperkows/=PUBLICATIONS/PER/G1995/survey.pdf |access-date=2021-03-28 |url-status=live |archive-url=https://web.archive.org/web/20210328181709/http://web.cecs.pdx.edu/~mperkows/=PUBLICATIONS/PER/G1995/survey.pdf |archive-date=2021-03-28}} (188 pages)<!-- http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.89.4349&rep=rep1&type=pdf -->

* {{cite web |title=Publications in the First Twenty Years of Switching Theory and Logic Design |author-first1=Radomir S. |author-last1=Stanković |author-first2=Tsutomu |author-last2=Sasao |author-first3=Jaakko T. |author-last3=Astola |series=Tampere International Center for Signal Processing (TICSP) Series |id=#14 |issn=1456-2774 |___location=Tampere University of Technology / TTKK, Monistamo, Finland |date=August 2001 |s2cid=62319288 |url=http://ticsp.cs.tut.fi/images/a/a5/Stari-radovi-report.pdf |access-date=2021-03-28 |url-status=live |archive-url=https://web.archive.org/web/20170809064702/http://ticsp.cs.tut.fi/images/a/a5/Stari-radovi-report.pdf |archive-date=2017-08-09}} (4+60 pages)

{{digital electronics}}