Architecture Design and Assessment System: Difference between revisions

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{{OrphanMore footnotes needed|date=FebruaryJanuary 20092022}}

The '''Architecture Design and Assessment System''' ('''ADAS''') was a set of software programs offered by the [[Research Triangle Institute]] from the mid -1980s until the early 1990s.<ref>G.A. Frank, D.L. Franke, and W.F. Ingogly, "An Architecture Design and Assessment System,"VLSI Design, Vol. 6, No. 8, Aug. 1985, pp. 30-50</ref>

the early 1990s.<ref>G.A. Frank, D.L. Franke, and W.F. Ingogly, "An Architecture Design and Assessment System,"VLSI Design, Vol. 6, No. 8, Aug. 1985, pp. 30-50</ref>

A [[petri net]]-like graph model of a system was graphically created. The hierarchical graphs were simulated to determine resource utilization and throughput. Functional simulation of the model could be realized by attaching [[C (programming language)|C]] or [[Ada (programming language)|Ada]] code to the nodes. This enabled dynamic resource assignment, timing, and priority.

A [[petri net]]-like graph model of a system was graphically created.

The hierarchical graphs were simulated to determine resource utilization and throughput. Functional simulation of the model could be realized by attaching [[C (programming language)]] or [[Ada (programming language)]] code to the nodes. This enabled dynamic resource assignment, timing, and priority.

==Simulation Model==

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An ADAS model consisted of nodes connected by directed arcs.

For abstract simulation a node represents a [[process (systems engineering)]] in the system that youis arebeing modelingmodeled. The readiness for execution or firing of this process requires that: its inputs are satisfied, space is available for its outputs, and its shared resource/hardware is available. During execution the node consumes its inputs, uses the resource for the prescribed duration, then produces its outputs.

The inputs and outputs of a process are represented by discrete tokens. These tokens flow along the arcs in the graph. If the maximum arc size is greater thatthan one, then an arc would represent a buffer between system processes.

To refine the model of the system, a subgraph could be placed below the node to refine the behavior of that process.

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* [http://portal.acm.org/citation.cfm?id=317825.317921 An Architecture Design and Assessment System for Software/Hardware Codesign, Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985]

* [http://www.informatik.uni-hamburg.de/TGI/pnbib/z/zobrist_g_w1.html The Modified Computational Graph and its Usage in Concurrent System Design and Analysis, Proc. of the Fifth Int. Conf. on Systems Engineering, pages 385-388. New York: IEEE, 1987]

* [httphttps://ieeexplore.ieee.org/Xploredocument/login.jsp?url=117945/iel2/152/3398/00117945.pdf?arnumber=117945 The Modelling of a Spaceflight Optical Disk Recorder Controller Using the Architecture Design and Assessment System, IEEE Southeast Con, Apr 1990]

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/145/5237/00203146.pdf?arnumber=203146 Application of Structured Analysis to a Telerobotic System, IEEE InternationInternational Conference on System Engineering, Aug 1990]{{dead link|date=January 2025|bot=medic}}{{cbignore|bot=medic}}

* [https://web.archive.org/web/20110517182337/http://www.aiaa.org/content.cfm?pageid=406&gTable=mtgpaper&gID=63108 Multiprocessor Performance Modeling with ADAS, AIAA Computers in Aerospace Conference, 7th, Monterey, CA, Oct 3-5, 1989]

* [https://web.archive.org/web/20110517182353/http://www.aiaa.org/content.cfm?pageid=406&gTable=mtgpaper&gID=63109 Modeling and Analysis of Multiprocessor Architectures, AIAA-1989-3014]

* [http://doi.ieeecomputersociety.org/10.1109/2.25383 The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability, IEEE Computer Apr. 1989]

* Integration of Tools for the Design and Assessment of High-Performance, Highly Reliable Computing System (DAHPHRS) Phase 1, NASA Contract NAS1-17964, May 1992, page 141 httphttps://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19920019342_1992019342.pdf

* [httphttps://wwwdoi.springerlinkorg/10.com/content/j76l018u2kk752321007%2FBF00935213 CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench, The Journal of VLSI Signal Processing, Nov 1990]

* Integration of Tools for the Design and Assessment of High-Performance, Highly Reliable Computing System (DAHPHRS) Phase 1, NASA Contract NAS1-17964, May 1992, page 141 http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19920019342_1992019342.pdf

* [httphttps://ntrs.nasa.gov/search.jsp?R=36107&id=1&qs=Ne%3D41%26N%3D4294814590%26Ns%3DArchiveName%257C0 Aircraft design for mission performance using nonlinear multiobjective optimization methods, Journal of Aircraft (ISSN 0021-8669), vol. 27, Dec. 1990]

* [http://www.springerlink.com/content/j76l018u2kk75232 CSP-based object-oriented description and simulation of a reconfigurable adaptive beamforming architecture using the OODRA workbench, The Journal of VLSI Signal Processing, Nov 1990]

* [http://ntrs.nasa.gov/search.jsp?R=36107&id=1&qs=Ne%3D41%26N%3D4294814590%26Ns%3DArchiveName%257C0 Aircraft design for mission performance using nonlinear multiobjective optimization methods, Journal of Aircraft (ISSN 0021-8669), vol. 27, Dec. 1990]

* [http://portal.acm.org/citation.cfm?doid=210330.210333 Parallelism in Sequential Multiprocessor Simulation Models: a Case Study, ACM Transactions on Modeling and Computer Simulation, Apr. 1995]

* The Practice of Prolog: a Prolog-based VLSI editor, Leon Sterling, 1990, {{ISBN 0262193019|0-262-19301-9}}

* [httphttps://ieeexplore.ieee.org/Xploredocument/login.jsp?url=230671/iel2/640/5940/00230671.pdf?tp=&isnumber=&arnumber=230671 Design Automation Technology for Codesign: Status and Directions, 1992 IEEE International Symposium on Circuits and Systems]

* The Practice of Prolog: a Prolog-based VLSI editor, Leon Sterling, 1990, ISBN 0262193019

* [httphttps://ieeexplore.ieee.org/Xploredocument/login.jsp?url=165823/iel2/566/4267/00165823.pdf?arnumber=165823 Aladdin Software Support, Proceedings of the IEEE 1991 National Aerospace and Electronics Conference]

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/640/5940/00230671.pdf?tp=&isnumber=&arnumber=230671 Design Automation Technology for Codesign: Status and Directions,1992 IEEE International Symposium on Circuits and Systems]

* Performance Analysis of a Large-Grain Dataflow Scheduling Paradigm, NASA Langley, June 1993, page 8 httphttps://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19930023024_1993023024.pdf

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/566/4267/00165823.pdf?arnumber=165823 Aladdin Software Support, Proceedings of the IEEE 1991 National Aerospace and Electronics Conference]

* [httphttps://ieeexplore.ieee.org/Xploredocument/login.jsp?url=111315/iel2/168/3349/00111315.pdf?arnumber=111315 Automated Fault Tolerance Evaluator for System Design, Simulation, and Analysis, Proceedings., IEEE/AIAA/NASA 9th Digital Avionics Systems Conference, 1990]

* Virtual Prototyping, Digital Signal Processing Systems, 1998 Lockheed Martin Technology Symposium, slide 7 https://web.archive.org/web/20110904153705/http://www.atl.lmco.com/projects/csim/vp4C.pdf

* Performance Analysis of a Large-Grain Dataflow Scheduling Paradigm, NASA Langley, June 1993, page 8 http://ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/19930023024_1993023024.pdf

* [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel2/168/3349/00111315.pdf?arnumber=111315 Automated Fault Tolerance Evaluator for System Design, Simulation, and Analysis, Proceedings., IEEE/AIAA/NASA 9th Digital Avionics Systems Conference, 1990]

* Virtual Prototyping, Digital Signal Processing Systems, 1998 Lockheed Martin Technology Symposium, slide 7 http://www.atl.lmco.com/projects/csim/vp4C.pdf

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