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BIOS NVRAM can include BIOS setup data and hardware configuration data (such as cached SPD and cached PCIE configuration space). |
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The CMOS RAM and the real-time clock have been integrated as a part of the [[Southbridge (computing)|southbridge]] chipset and they may not be standalone chips on modern motherboards.<ref name="100Series">{{cite web|url=http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html |title=Intel 100 Series Chipset Family PCH Datasheet| publisher=Intel |date=August 2015 |access-date=16 April 2016}}</ref><ref>{{cite web|url=https://www.intel.com/Assets/PDF/datasheet/290562.pdf|title=82430FX PCISET Data Sheet|publisher=Intel|access-date=23 January 2023}}</ref> In turn, the southbridge has been integrated into a single [[Platform Controller Hub]]. Alternatively BIOS settings may be stored in the computer's [[Super I/O]] chip.<ref>{{cite book | url=https://books.google.com/books?id=E1p2FDL7P5QC&dq=bios+cmos&pg=PA393 | title=Upgrading and Repairing PCS | isbn=978-0-7897-2974-3 | last1=Mueller | first1=Scott | date=2004 | publisher=Que }}</ref>
The chipset built-in NVRAM capacity is typically 256 [[byte]]s.<ref name="100Series" /> For this reason, later BIOS implementations may use a small portion of BIOS flash ROM as NVRAM, to store BIOS setup and hardware configuration data.<ref>{{Cite web| title=AMIBIOS8 Flash Update & BIOS Recovery Methods | url=http://rom.by/files/AMIBIOS8-Flash-Recovery-Whitepaper.pdf
Today's [[UEFI]] motherboards use [[NVRAM]] to store configuration data (NVRAM is a portion of the UEFI [[Flash memory|flash]] ROM), but by many [[OEM]]s' design, the UEFI settings are still lost if the CMOS battery fails.<ref>{{Cite web|title=UEFI NVRAM - OSDev Wiki|url=https://wiki.osdev.org/UEFI_NVRAM|access-date=2020-09-11|website=wiki.osdev.org|df=dmy-all}}</ref><ref>{{Cite book|chapter-url=https://media.springernature.com/original/springer-static/image/chp%3A10.1007%2F978-1-4842-6106-4_4/MediaObjects/488723_1_En_4_Fig6_HTML.png|doi = 10.1007/978-1-4842-6106-4_4|chapter = Firmware Resiliency: Detection|title = Building Secure Firmware|year = 2020|last1 = Yao|first1 = Jiewen|last2 = Zimmer|first2 = Vincent|pages = 115–162|isbn = 978-1-4842-6105-7| s2cid=242541772 }}</ref>
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