Dynamic frequency scaling: Difference between revisions

Revision as of 12:47, 6 December 2021

Latest revision as of 12:28, 3 June 2025

(16 intermediate revisions by 11 users not shown)

Line 1:

{{Short description|Power management technique in computers}}

{{for|the CPU design principle|Frequency scaling}}

{{redirect|CPU throttling|other uses|Throttle (disambiguation)#Computing}}

Line 7 ⟶ 8:

'''Dynamic frequency scaling''' (also known as '''CPU throttling''') is a [[power management]] technique in [[computer architecture]] whereby the [[Clock rate|frequency]] of a microprocessor can be automatically adjusted "on the fly" depending on the actual needs, to [[Power management integrated circuit|conserve power]] and reduce the amount of heat generated by the chip. Dynamic frequency scaling helps preserve battery on mobile devices and decrease cooling cost and noise on [[Quiet PC|quiet computing settings]], or can be useful as a security measure for overheated systems (e.g. after poor [[overclocking]]).

Dynamic frequency scaling almost always appear in conjunction with [[dynamic voltage scaling]], since lowerhigher frequencies require lowerhigher supply voltages for the digital circuit to yield correct results. The combined topic is known as '''dynamic voltage and frequency scaling''' ('''DVFS''').

Processor throttling is also known as "automatic [[underclocking]]". Automatic [[overclocking]] (boosting) is also technically a form of dynamic frequency scaling, but it's relatively new and usually not discussed with throttling.

== Operation ==

{{see also|Processor power dissipation#Sources}}

The dynamic power (''[[switching power]]'') dissipated per unit of time by a chip is ''C·V²·A·f'', where C is the [[capacitance]] being switched per clock cycle, V is [[voltage]], A is the Activity''activity Factorfactor''<ref name="ActivityFactor">{{cite journal | title = Timing-aware power-optimal ordering of signals | author = K. Moiseev, A. Kolodny and S. Wimer | journal = ACM Transactions on Design Automation of Electronic Systems |volume=13 |issue=4 |date=September 2008| pages = 1–17 | doi = 10.1145/1391962.1391973 | s2cid = 18895687 }}</ref> indicating the average number of switching events undergoneper clock cycle by the transistors in the chip (as a unit-lessunitless quantity) and f is the switchingclock frequency.<ref>{{Cite book|first=J. M.|last= Rabaey|title= Digital Integrated Circuits|publisher= Prentice Hall|year= 1996}}</ref>

Voltage is therefore the main determinant of power usage and heating.<ref>{{cite web|url=https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|author= Victoria Zhislina|date=2014-02-19|title=Why has CPU frequency ceased to grow?|publisher=Intel}}</ref> The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced.<ref>https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf {{Bare URL PDF|date=March 2022}}</ref> Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of a piece of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimalminimized.<ref>{{cite arxivarXiv | title = The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices |year=2014 | eprint = 1401.4655|author1=Karel De Vogeleer |last2=Memmi |first2=Gerard |last3=Jouvelot |first3=Pierre |last4=Coelho |first4=Fabien |class=cs.OH }}</ref>

[[Subthreshold leakage|Leakage current]] has become more and more important as transistor sizes have become smaller and threshold voltage levels lowerare reduced. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, [[High-κ dielectric|high-k metal-gates]] and power gating have been common methods.

[[Dynamic voltage scaling]] is another related power conservation technique that is often used in conjunction with frequency scaling, as the frequency that a chip may run at is related to the operating voltage.

The efficiency of some electrical components, such as voltage regulators, decreases with increasing temperature, so the power usage may increase with temperature. Since increasing power use may increase the temperature, increases in voltage or frequency may increase system power demands even further than the CMOS formula indicates, and vice versa.<ref>{{cite web | url = http://www.silentpcreview.com/article821-page5.html | title = Asus EN9600GT Silent Edition Graphics Card | author = Mike Chin | page = 5 | work = Silent PC Review | access-date = 21 April 2008}}</ref><ref name="SPCRNewLevels">{{cite web | url = http://www.silentpcreview.com/article814-page1.html | title = 80 Plus expands podium for Bronze, Silver & Gold | author = Mike Chin | work = Silent PC Review | date = 19 March 2008 | access-date = 21 April 2008 }}</ref>

== {{Anchor|ACPI|CPPC}} Standard interface ==

[[ACPI]] 1.0 (1996) defines a way for a CPU to go to idle "C states", but defines no frequency-scaling system.

ACPI 2.0 (2000) introduces a system of ''P states'' (power-performance states) that a processor can use to communicate its possible frequency&ndash;power settings to the OS. The operating system then sets the speed as needed by switching between these states. Throttling technology such as SpeedStep, PowerNow!/Cool'n'Quiet, and PowerSaver all work through P states. There is a limit of 16 states maximum.<ref>{{cite web

| url = http://www.acpi.info/DOWNLOADS/ACPIspec30.pdf

| title = Advanced Configuration and Power Interface Specification, Revision&nbsp;3.0, Section&nbsp;2.6 Device and Processor Performance State Definitions

| date = 2004-09-02

| access-date = 2015-08-19

| website = ACPI.info

| page = 23

| archive-date = November 28, 2015

| archive-url = https://web.archive.org/web/20151128143452/http://www.acpi.info/DOWNLOADS/ACPIspec30.pdf

| url-status = dead

}}</ref>

ACPI 5.0 (2011) introduces collaborative processor performance control (CPPC), exposing hundreds of performance levels to the OS for selection in the form of a "performance level" abstracted away from the frequency. This abstraction provides some leeway for the processor to adjust its workings in ways other than just the frequency.<ref>{{cite web |title=Collaborative Processor Performance Control (CPPC) — The Linux Kernel documentation |url=https://www.kernel.org/doc/html/latest/admin-guide/acpi/cppc_sysfs.html |website=www.kernel.org}}</ref><ref>{{cite web |title=8.4. Declaring Processors |url=https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#collaborative-processor-performance-control |website=ACPI Specification 6.4 documentation}}</ref><ref>{{cite web |title=Overview about power and performance tuning for the Windows Server |url=https://learn.microsoft.com/en-us/windows-server/administration/performance-tuning/hardware/power/power-performance-tuning |website=learn.microsoft.com |language=en-us |date=29 August 2022}}</ref>

== Autonomous frequency scaling ==

Voltage is therefore the main determinant of power usage and heating.<ref>{{cite web|url=https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|author= Victoria Zhislina|date=2014-02-19|title=Why has CPU frequency ceased to grow?|publisher=Intel}}</ref> The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced.<ref>https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf</ref> Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of a piece of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimal.<ref>{{cite arxiv | title = The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices |year=2014 | eprint = 1401.4655|author1=Karel De Vogeleer |last2=Memmi |first2=Gerard |last3=Jouvelot |first3=Pierre |last4=Coelho |first4=Fabien |class=cs.OH }}</ref>

[[Subthreshold leakage|Leakage current]] has become more and more important as transistor sizes have become smaller and threshold voltage levels lower. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, [[High-κ dielectric|high-k metal-gates]] and power gating have been common methods.

A number of modern CPUs can perform frequency scaling autonomously, using a performance level range and a "efficiency/performance preference" hint from the OS.

[[Dynamic voltage scaling]] is another related power conservation technique that is often used in conjunction with frequency scaling, as the frequency that a chip may run at is related to the operating voltage.

* Intel CPUs starting with [[Skylake (microarchitecture)|Skylake]] support ''hardware-managed P-states'' aka ''Speed Shift'', It based on CPPC protocol, and it using [[model-specific register]] as the control channel.<ref>{{man|8|x86_energy_perf_policy|Linux}}</ref><ref>{{cite web |title=intel_pstate CPU Performance Scaling Driver — The Linux Kernel documentation |url=https://www.kernel.org/doc/html/v4.19/admin-guide/pm/intel_pstate.html |website=www.kernel.org}}</ref>

The efficiency of some electrical components, such as voltage regulators, decreases with increasing temperature, so the power usage may increase with temperature. Since increasing power use may increase the temperature, increases in voltage or frequency may increase system power demands even further than the CMOS formula indicates, and vice versa.<ref>{{cite web | url = http://www.silentpcreview.com/article821-page5.html | title = Asus EN9600GT Silent Edition Graphics Card | author = Mike Chin | page = 5 | work = Silent PC Review | access-date = 21 April 2008}}</ref><ref name="SPCRNewLevels">{{cite web | url = http://www.silentpcreview.com/article814-page1.html | title = 80 Plus expands podium for Bronze, Silver & Gold | author = Mike Chin | work = Silent PC Review | access-date = 21 April 2008 }}</ref>

* AMD CPUs starting with [[Zen 2]] supports a similar feature. It depends on CPPC being enabled. The preferred communication channel is a MSR (different from the Intel one) introduced in Zen 3; Zen 2 units use the ACPI AML method.<ref>{{cite web |title=amd-pstate CPU Performance Scaling Driver — The Linux Kernel documentation |url=https://docs.kernel.org/admin-guide/pm/amd-pstate.html |website=docs.kernel.org}}</ref>

==Performance impact==

Line 34 ⟶ 57:

=== Intel ===

[[Intel]]'s CPU throttling technology, [[SpeedStep]], is used in its mobile and desktop CPU lines.

=== AMD ===