Dynamic frequency scaling: Difference between revisions

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{{Short description|Power management technique in computers}}

{{for|the CPU design principle|Frequency scaling}}

{{redirect|CPU throttling|other uses|Throttle (disambiguation)#Computing}}

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Dynamic frequency scaling almost always appear in conjunction with [[dynamic voltage scaling]], since higher frequencies require higher supply voltages for the digital circuit to yield correct results. The combined topic is known as '''dynamic voltage and frequency scaling''' ('''DVFS''').

Processor throttling is also known as "automatic [[underclocking]]". Automatic [[overclocking]] (boosting) is also technically a form of dynamic frequency scaling, but it's relatively new and usually not discussed with throttling.

== Operation ==

{{see also|Processor power dissipation#Sources}}

The dynamic power (''[[switching power]]'') dissipated by a chip is ''C·V²·A·f'', where C is the [[capacitance]] being switched per clock cycle, V is [[voltage]], A is the Activity''activity Factorfactor''<ref name="ActivityFactor">{{cite journal | title = Timing-aware power-optimal ordering of signals | author = K. Moiseev, A. Kolodny and S. Wimer | journal = ACM Transactions on Design Automation of Electronic Systems |volume=13 |issue=4 |date=September 2008| pages = 1–17 | doi = 10.1145/1391962.1391973 | s2cid = 18895687 }}</ref> indicating the average number of switching events per clock cycle by the transistors in the chip (as a unitless quantity) and f is the clock frequency.<ref>{{Cite book|first=J. M.|last= Rabaey|title= Digital Integrated Circuits|publisher= Prentice Hall|year= 1996}}</ref>

Voltage is therefore the main determinant of power usage and heating.<ref>{{cite web|url=https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|author= Victoria Zhislina|date=2014-02-19|title=Why has CPU frequency ceased to grow?|publisher=Intel}}</ref> The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and can be reduced if the frequency is also reduced.<ref>https://www.usenix.org/legacy/events/hotpower/tech/full_papers/LeSueur.pdf {{Bare URL PDF|date=March 2022}}</ref> Dynamic power alone does not account for the total power of the chip, however, as there is also static power, which is primarily because of various leakage currents. Due to static power consumption and asymptotic execution time it has been shown that the energy consumption of software shows convex energy behavior, i.e., there exists an optimal CPU frequency at which energy consumption is minimized.<ref>{{cite arXiv | title = The Energy/Frequency Convexity Rule: Modeling and Experimental Validation on Mobile Devices |year=2014 | eprint = 1401.4655|author1=Karel De Vogeleer |last2=Memmi |first2=Gerard |last3=Jouvelot |first3=Pierre |last4=Coelho |first4=Fabien |class=cs.OH }}</ref>

[[Subthreshold leakage|Leakage current]] has become more and more important as transistor sizes have become smaller and threshold voltage levels are reduced. A decade ago, dynamic power accounted for approximately two-thirds of the total chip power. The power loss due to leakage currents in contemporary CPUs and SoCs tend to dominate the total power consumption. In the attempt to control the leakage power, [[High-κ dielectric|high-k metal-gates]] and power gating have been common methods.

[[Dynamic voltage scaling]] is another related power conservation technique that is often used in conjunction with frequency scaling, as the frequency that a chip may run at is related to the operating voltage.

The efficiency of some electrical components, such as voltage regulators, decreases with increasing temperature, so the power usage may increase with temperature. Since increasing power use may increase the temperature, increases in voltage or frequency may increase system power demands even further than the CMOS formula indicates, and vice versa.<ref>{{cite web | url = http://www.silentpcreview.com/article821-page5.html | title = Asus EN9600GT Silent Edition Graphics Card | author = Mike Chin | page = 5 | work = Silent PC Review | access-date = 21 April 2008}}</ref><ref name="SPCRNewLevels">{{cite web | url = http://www.silentpcreview.com/article814-page1.html | title = 80 Plus expands podium for Bronze, Silver & Gold | author = Mike Chin | work = Silent PC Review | date = 19 March 2008 | access-date = 21 April 2008 }}</ref>

== {{Anchor|ACPI|CPPC}} Standard interface ==

[[ACPI]] 1.0 (1996) defines a way for a CPU to go to idle "C states", but defines no frequency-scaling system.

ACPI 2.0 (2000) introduces a system of ''P states'' (power-performance states) that a processor can use to communicate its possible frequency&ndash;power settings to the OS. The operating system then sets the speed as needed by switching between these states. Throttling technology such as SpeedStep, PowerNow!/Cool'n'Quiet, and PowerSaver all work through P states. There is a limit of 16 states maximum.<ref>{{cite web

| url = http://www.acpi.info/DOWNLOADS/ACPIspec30.pdf

| title = Advanced Configuration and Power Interface Specification, Revision&nbsp;3.0, Section&nbsp;2.6 Device and Processor Performance State Definitions

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}}</ref>

ACPI 5.0 (2011) introduces collaborative processor performance control (CPPC)., Insteadexposing hundreds of askingperformance forlevels a specific performance level,to the OS onlyfor sendsselection ain hintthe form of reletaivea "performance/power preference,level" leavingabstracted away from the CPUfrequency. toThis doabstraction itsprovides ownsome frequencyleeway selection.for Windowsthe andprocessor Linuxto offeradjust supportits forworkings CPPCin onways newerother AMDthan andjust Intelthe CPUsfrequency.<ref>{{cite web |title=Collaborative Processor Performance Control (CPPC) — The Linux Kernel documentation |url=https://www.kernel.org/doc/html/latest/admin-guide/acpi/cppc_sysfs.html |website=www.kernel.org}}</ref><ref>{{cite web |title=8.4. Declaring Processors |url=https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/08_Processor_Configuration_and_Control/declaring-processors.html#collaborative-processor-performance-control |website=ACPI Specification 6.4 documentation}}</ref><ref>{{cite web |title=Overview about power and performance tuning for the Windows Server |url=https://learn.microsoft.com/en-us/windows-server/administration/performance-tuning/hardware/power/power-performance-tuning |website=learn.microsoft.com |language=en-us |date=29 August 2022}}</ref>

== Autonomous frequency scaling ==

A number of modern CPUs can perform frequency scaling autonomously, using a performance level range and a "efficiency/performance preference" hint from the OS.

* Intel CPUs starting with [[Skylake (microarchitecture)|Skylake]] support ''hardware-managed P-states'' aka ''Speed Shift'', It based on CPPC protocol, and it using [[model-specific register]] as the control channel.<ref>{{man|8|x86_energy_perf_policy|Linux}}</ref><ref>{{cite web |title=intel_pstate CPU Performance Scaling Driver — The Linux Kernel documentation |url=https://www.kernel.org/doc/html/v4.19/admin-guide/pm/intel_pstate.html |website=www.kernel.org}}</ref>

* AMD CPUs starting with [[Zen 2]] supports a similar feature. It depends on CPPC being enabled. The preferred communication channel is a MSR (different from the Intel one) introduced in Zen 3; Zen 2 units use the ACPI AML method.<ref>{{cite web |title=amd-pstate CPU Performance Scaling Driver — The Linux Kernel documentation |url=https://docs.kernel.org/admin-guide/pm/amd-pstate.html |website=docs.kernel.org}}</ref>

==Performance impact==