Latency oriented processor architecture: Difference between revisions

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==Flynn's taxonomy==
{{Main|Flynn's taxonomy}}
LatencyTypically, latency oriented processor architectures wouldexecute normallya fallsingle intotask theoperating categoryon ofa single data stream, and so they are [[Single instruction, single data|SISD]] classification under flynnFlynn's taxonomy. This implies a typical characteristic of latencyLatency oriented processor architectures ismight toalso executeinclude a[[Single singleinstruction, task operating on a singlemultiple data stream. Some [[|SIMD]] styleinstruction multimediaset extensions of popular instruction sets, such as Intel [[MMX (instruction set)|MMX]] and [[Streaming SIMD Extensions|SSE]] instructions, should also fall under the category of latency oriented processor architectures;<ref name=YanSohilin2016/>even because,though althoughthese theyextensions operate on a large data setsets, their primary goal is also to reduce overall latency.<ref for the entire task at hand.name=YanSohilin2016/>
 
==Implementation techniques==
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===Instruction set architecture (ISA)===
{{Main|Instruction set}}
Most architectures today use shorter and simpler instructions, like the [[load/store architecture]], which help in optimizing the instruction pipeline for faster execution. Instructions are usually all of the same size which also helps in optimizing the instruction fetch logic. Such an ISA is called a [[Reduced instruction set computing|RISC]] architecture.<ref>{{cite conference|last1=Bhandarkar|first1=Dileep|last2=Clark|first2=Douglas W. |title=PerformanceProceedings fromof Architecture:the Comparingfourth ainternational RISCconference andon aArchitectural CISCsupport withfor programming languages and operating systems Similar- HardwareASPLOS-IV Organization|journalchapter=ProceedingsPerformance offrom thearchitecture: FourthComparing Internationala ConferenceRISC onand Architecturala SupportCISC forwith Programmingsimilar Languages andhardware Operatingorganization Systems|date=1 January 1991|pages=310–319|doi=10.1145/106972.107003|url=http://dl.acm.org/citation.cfm?id=107003&CFID=860927590&CFTOKEN=39315780|publisher=ACM|isbn=0897913809 |doi-access=free}}</ref>
 
===Instruction pipelining===