Pass transistor logic: Difference between revisions

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{{Short description|Group of logic families in electronics}}

In [[electronics]], '''pass transistor logic''' (PTL) describes several [[logic family|logic families]] used in the design of [[integrated circuit]]s. It reduces the count of [[transistor|transistors]] used to make different [[logic gate]]s, by eliminating redundant transistors. Transistors are used as switches to pass [[logic level]]s between nodes of a circuit, instead of as switches connected directly to supply voltages.<ref>{{cite book |first1=Jaume |last1=Segura |first2=Charles F. |last2=Hawkins |title=CMOS electronics: how it works, how it fails |publisher=Wiley-IEEE |date=2004 |isbn=0-471-47669-2 |pages=132 |url=}}</ref> This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage (since pass transistors have some resistance and do not provide level restoration). Each transistor in series is less saturated at its output than at its input.<ref>{{cite book |first=Clive |last=Maxfield |title=Bebop to the boolean boogie: an unconventional guide to electronics |publisher=Newnes |date=2008 |isbn=978-1-85617-507-4 |pages=423–6 |url=}}</ref> If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional [[CMOS logic]] switches transistors so the output connects to one of the power supply rails (resembling an [[open collector]] scheme), so logic voltage levels in a sequential chain do not decrease.

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=={{anchor|CPL}}Complementary pass transistor logic==

Some authors use the term "''complementary pass transistor logic"'' to indicate a style of implementing logic gates that uses [[transmission gate]]s composed of both NMOS and PMOS pass transistors.<ref>

{{cite book |first=Gary K. |last=Yeap |title=Practical Low Power Digital VLSI Design |publisher=Springer |orig-year=1998 |date=2012 |isbn=978-1-4615-6065-4 |pages=197 |url=https://books.google.com/books?id=sXTdBwAAQBAJ}}

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Other authors use the term "''complementary pass transistor logic"'' (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter.<ref>

{{cite book |first=Vojin G. |last=Oklobdzija |title=Digital Design and Fabrication |publisher= CRC Press|date= 19 December 2017|isbn= 9780849386046|pages=2–39 |url=https://books.google.com/books?id=VOnyWUUUj04C}}

</ref><ref name="IEEE_1990"/><ref name="ULVD_2015"/>

OtherYet other authors use the term "''complementary pass transistor logic"'' (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters.<ref>

{{cite book |editor-first=Wai-Kai |editor-last=Chen |title=Logic Design |publisher=CRC Press |___location= |date=2003 |isbn=978-0-203-01015-0 |pages=15–7 |url=https://books.google.com/books?id=X0a3BgAAQBAJ |oclc=1029500642}}

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</ref>

''Complementary pass transistor logic'' or "Differential''differential pass transistor logic" refers'' to a [[logic families|logic family]] which is designed for certain advantage. It is common to use this logic family for [[Multiplexer#Digital multiplexers|multiplexers]] and [[Latch (electronics)|latches]].{{citation needed|date=April 2015}}

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an [[Inverter (logic gate)|inverter]] . The CMOS [[transmission gate]]s consist of nMOS and pMOS transistor connected in parallel.

==Other forms==