Pass transistor logic: Difference between revisions

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{{Short description|Group of logic families in electronics}}

{{cleanup|date =October 2010}}

In [[electronics]], '''pass transistor logic''' (PTL) describes several [[logic family|logic families]] used in the design of [[integrated circuit]]s. It reduces the count of [[transistor|transistors]] used to make different [[logic gate]]s, by eliminating redundant transistors. Transistors are used as switches to pass [[logic level]]s between nodes of a circuit, instead of as switches connected directly to supply voltages.<ref>{{cite book |first1=Jaume |last1=Segura, |first2=Charles F. |last2=Hawkins ''|title=CMOS electronics: how it works, how it fails'', |publisher=Wiley-IEEE, |date=2004 ISBN |isbn=0-471-47669-2, page |pages=132 |url=}}</ref> This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage (since pass transistors have some resistance and do not provide level restoration). Each transistor in series is less saturated at its output than at its input.<ref>{{cite book |first=Clive |last=Maxfield ''|title=Bebop to the boolean boogie: an unconventional guide to electronics'' |publisher=Newnes, |date=2008 ISBN |isbn=978-1-85617-507-3,4 |pages=423–6 pp. 423-426|url=}}</ref> If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional [[CMOS logic]] switches transistors so the output connects to one of the power supply rails (resembling an [[open collector]] scheme), so logic voltage levels in a sequential chain do not decrease.

<!-- needs a diagram -->

In [[electronics]], '''pass transistor logic''' (PTL) describes several [[logic family|logic families]] used in the design of [[integrated circuit]]s. It reduces the count of transistors used to make different [[logic gate]]s, by eliminating redundant transistors. Transistors are used as switches to pass [[logic level]]s between nodes of a circuit, instead of as switches connected directly to supply voltages.<ref>Jaume Segura, Charles F. Hawkins ''CMOS electronics: how it works, how it fails'', Wiley-IEEE, 2004 ISBN 0-471-47669-2, page 132</ref> This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage. Each transistor in series is less saturated at its output than at its input.<ref>Clive Maxfield ''Bebop to the boolean boogie: an unconventional guide to electronics''Newnes, 2008 ISBN 1-85617-507-3, pp. 423-426</ref> If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional [[CMOS logic]] switches transistors so the output connects to one of the power supply rails, so logic voltage levels in a sequential chain do not decrease.

<!-- needs a diagram -->Simulation of circuits may be required to ensure adequate performance.

== Applications ==

[[Image:SRAM Cell (6 Transistors).svg|thumb|250px|A six-transistor CMOS [[Static random-access memory | SRAM ]] cell. M5 and M6 are bidirectional pass transistors.]]

[[Image:Multiplexer-based latch using transmission gates.svg|thumb|250px|a 10-transistor CMOS [[ flip-flop (electronics)#Gated D latch | gated D latch]], similar to the ones in the CD4042 or the CD74HC75 integrated circuits. ]]

Pass transistor logic often uses fewer transistors, runs faster, and requires less power than the same function implemented with the same transistors in fully complementary CMOS logic.<ref>

Norimitsu Sako.

[httphttps://wwwpatents.google.com/patentspatent/US7171636 "Patent US7171636: Pass-transistor logic circuit and a method of designing thereof"].

'It is known in the art to employ a "pass-transistor logic circuit" to reduce a number of elements and power consumption, and to improve operating speed.'

</ref>

XOR has the worst-case [[Karnaugh map]]—if implemented from simple gates, it requires more transistors than any other function. Back when transistors were more expensive, designers of the [[Z80]] and many other chips were motivated to save a few transistors by implementing the XOR using pass-transistor logic rather than simple gates.<ref>

XOR has the worst-case [[Karnaugh map]] --

{{cite web |first=Ken |last=Shirriff

if implemented from simple gates, it requires more transistors

[ |url=http://www.righto.com/2013/09/understanding-z-80-processor-one-gate.html "|title=Reverse-engineering the Z-80: the silicon for two interesting gates explained"]. |date=2013}}

than any other function.

The designers of the [[Z80]] and many other chips save a few transistors by implementing the

XOR using pass-transistor logic

rather than simple gates.<ref>

Ken Shirriff.

[http://www.righto.com/2013/09/understanding-z-80-processor-one-gate.html "Reverse-engineering the Z-80: the silicon for two interesting gates explained"].

2013.

</ref>

==Basic principles of pass transistor circuits==

MOSFET pass transistors are [[Electronic switch|electronic switches]] that turn on or off the path between their drain and source depending on their gate's voltage signal (for instance the clock signal in the [[Static random-access memory|SRAM]] cell or [[gated D latch]]).

The pass transistor is driven by a periodic clock signal and acts as an access switch to either charge up or charge down the parasitic capacitance C_''x'', depending on the input signal V_''in''. Thus, the two possible operations when the clock signal is active (CK = 1) are the logic "1" transfer (charging up the capacitance C_''x'' to a logic-high level) and the logic "0" transfer (charging down the capacitance C_''x'' to a logic-low level). In either case, the output of the depletion load nMOS inverter obviously assumes a logic-low or a logic-high level, depending upon the voltage V_''x''.

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Because pass transistors do not provide level restoration and because their conducting path has a small non-zero resistance, there is increased [[RC delay]] for charging the next logic stage's input capacitance (which includes parasitic capacitance in addition to the next stage's gate capacitance) towards valid logic-high or logic-low voltage levels.

==Complementary pass transistor logic==

Simulation of circuits may be required to ensure adequate performance.

Some authors use the term "complementary pass transistor logic" to indicate a style of implementing logic gates that uses [[transmission gate]]s composed of both NMOS and PMOS pass transistors.<ref>

Gary K. Yeap.

[https://books.google.com/books?id=sXTdBwAAQBAJ "Practical Low Power Digital VLSI Design"].

2012.

p. 197.

</ref>

=={{anchor|CPL}}Complementary pass transistor logic==

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter.<ref>

Vojin G. Oklobdzija.

Some authors use the term "''complementary pass transistor logic"'' to indicate a style of implementing logic gates that uses [[transmission gate]]s composed of both NMOS and PMOS pass transistors.<ref>

[https://books.google.com/books?id=VOnyWUUUj04C "Digital Design and Fabrication"].

{{cite book |first=Gary K. |last=Yeap |title=Practical Low Power Digital VLSI Design |publisher=Springer |orig-year=1998 |date=2012 |isbn=978-1-4615-6065-4 |pages=197 |url=https://books.google.com/books?id=sXTdBwAAQBAJ}}

p. 2-39.

</ref>

Other authors use the term "''complementary pass transistor logic"'' (CPL) to indicate a style of implementing logic gates usingwhere dual-raileach encoding.gate Everyconsists CPLof gatea hasNMOS-only twopass outputtransistor wiresnetwork, bothfollowed theby positivea signalCMOS and the complementary signal, eliminating the need foroutput invertersinverter.<ref>

{{cite book |first=Vojin G. |last=Oklobdzija |title=Digital Design and Fabrication |publisher= CRC Press|date= 19 December 2017|isbn= 9780849386046|pages=2–39 |url=https://books.google.com/books?id=VOnyWUUUj04C}}

Wai-Kai Chen.

</ref><ref name="IEEE_1990"/><ref name="ULVD_2015"/>

[https://books.google.com/books?id=X0a3BgAAQBAJ "Logic Design"].

2003.

OtherYet other authors use the term "''complementary pass transistor logic"'' (CPL) to indicate a style of implementing logic gates whereusing eachdual-rail gateencoding. consistsEvery ofCPL agate NMOS-onlyhas passtwo transistoroutput networkwires, followedboth bythe apositive CMOSsignal outputand the complementary signal, eliminating the need for inverterinverters.<ref>

p. 15-7.

{{cite book |editor-first=Wai-Kai |editor-last=Chen |title=Logic Design |publisher=CRC Press |___location= |date=2003 |isbn=978-0-203-01015-0 |pages=15–7 |url=https://books.google.com/books?id=X0a3BgAAQBAJ |oclc=1029500642}}

</ref><ref>

{{cite book |editor-first=Vojin G. |editor-last=Oklobdzija |title=The Computer Engineering Handbook |publisher=Taylor & Francis |___location= |date=2001 |isbn=978-0-8493-0885-7 |pages=2-23–2-24 |url=https://books.google.com/books?id=38Aj3CjHgc8C}}

Vojin G. Oklobdzija.

[https://books.google.com/books?id=38Aj3CjHgc8C "The Computer Engineering Handbook"].

2001.

p. 2-23 to 2-24.

</ref><ref>

{{cite book |first=Ajit |last=Pal |title=Low-Power VLSI Circuits and Systems |publisher=Springer |date=2014 |isbn=978-81-322-1937-8 |pages=109–110 |url=https://books.google.com/books?id=0I1xBQAAQBAJ |chapter=5.2.3 Pass-Transistor Logic Families |chapter-url={{GBurl|0I1xBQAAQBAJ|p=109}}}}

Ajit Pal.

[https://books.google.com/books?id=0I1xBQAAQBAJ "Low-Power VLSI Circuits and Systems"].

p. 109 to 110.

</ref>

''Complementary pass transistor logic'' or "Differential''differential pass transistor logic" refers'' to a [[logic families|logic family]] which is designed for certain advantage. It is common to use this logic family for [[Multiplexer#Digital multiplexers|multiplexers]] and [[Latch (electronics)|latches]].{{factcitation needed|date=April 2015}}

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an [[Inverter (logic gate)|inverter]] . The CMOS [[transmission gate]]s consist of nMOS and pMOS transistor connected in parallel.

''Complementary pass transistor logic'' or "Differential pass transistor logic" refers to a [[logic families|logic family]] which is designed for certain advantage. It is common to use this logic family for [[Multiplexer#Digital multiplexers|multiplexers]] and [[Latch (electronics)|latches]].{{fact|date=April 2015}}

CPL uses series transistors to select between possible inverted output values of the logic, the output of which drives an [[Inverter (logic gate)|inverter]] The CMOS [[transmission gate]]s consist of nMOS and pMOS transistor connected in parallel.

==Other forms==

Static and dynamic types of pass transistor logic exist, with differing properties with respect to speed, power and low-voltage operation.<ref>{{cite book |first=Cornelius T. |last=Leondes ''|title=Digital signal processing systems: implementation techniques'' |publisher=Elsevier, |date=1995 ISBN |isbn=0-12-012768-7 page |pages=2 |url=}}</ref> As integrated circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the number of sequential stages. Because complementary inputs are often required to control pass transistors, additional logic stages are required.

==References==

{{Reflist|2}}refs=

<ref name="IEEE_1990">{{cite journal |title=A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic |author-last1=Yano |author-first1=Kuniaki |author-last2=Yamanaka |author-first2=Toshiaki Yamanaka |author-last3=Nishida |author-first3=Takeshi |author-last4=Saito |author-first4=Mitsuo |author-last5=Shimohigashi |author-first5=Katsuhiro |author-last6=Shimizu |author-first6=Atsushi |date=1990 |journal=[[IEEE Journal of Solid-State Circuits]] |volume=25 |issue=2 |pages=388–395 |doi=10.1109/4.52161|bibcode=1990IJSSC..25..388Y }}</ref>

<ref name="ULVD_2015">{{cite book |title=Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits |first1=Nele |last1=Reynders |first2=Wim |last2=Dehaene |series=Analog Circuits And Signal Processing (ACSP) |date=2015 |publisher=Springer Switzerland |isbn=978-3-319-16135-8 |issn=1872-082X |doi=10.1007/978-3-319-16136-5 |lccn=2015935431}}</ref>

}}

==Further reading==

*{{cite book |last1=Weste and |last2=Harris, |title=CMOS VLSI Design, Third|year=2005 Edition|publisher= (ISBNPearson/Addison-Wesley|edition=3rd |isbn=0-321-14901-7; ISBN|pages= 0-321-26977-2 (international edition))|url=}}

*Douglas A. Pucknell and Kamran Eshraghian, Basic VLSI Design, Third Edition (ISBN 978-81-203-0986-9 (Indian Edition))

*{{cite book |first1=Douglas A. |last1=Pucknell |first2=Kamran |last2=Eshraghian |title=Basic VLSI Design |year=1994 |publisher= Prentice-Hall Of India Pvt. Limited|edition=3rd |isbn=978-81-203-0986-9 |pages= |url=}}

{{Logic Families}}

[[Category:Logic families]]